Technical Manager

Quest Global; Bengaluru; On-site; INR 2,500,000 - 5,500,000; Full time

Job summary

Quest Global in Bengaluru is seeking an experienced Full-Chip/Subsystem STA engineer to drive timing closure across multiple modes. You will validate constraints, clocks, and IO delays, then debug path-level timing and implement ECO actions.

The role requires deep understanding of timing models and cross-functional collaboration with RTL, synthesis and PnR teams. Ideal candidates have 5–10 years in STA with PrimeTime/Tempus, SDC expertise, and hands-on MCCM timing analysis capabilities, plus

Qualifications

• 5–10 years of STA/timing-closure experience at subsystem or full-chip level.
• Strong hands-on expertise with PrimeTime and/or Tempus.
• Good knowledge of SDC constraints and debugging timing issues.
• Experience with MCMM timing analysis and ECO generation.
• Understanding of parasitic extraction and LEC workflow.
• Exposure to EDA tools for timing correlation and sign-off readiness.

Responsibilities

• Drive full-chip or subsystem STA and timing closure across modes and corners.
• Validate constraints, clocks, generated clocks, and IO delays.
• Analyze setup/hold and clock-gating, perform path-level checks.
• Debug timing across interfaces and block paths, resolve constraint issues.
• Build timing models for hierarchical analysis and DOE timing closure.
• Generate timing ECO recommendations and coordinate with PnR teams.
• Support LEC, extraction correlation and QoR signoff readiness.
• Collaborate with RTL, synthesis, PnR and DFT teams to resolve root causes.

Skills

STA timing closure

PrimeTime

Tempus

SDC constraints

Path-based debugging

Timing ECO generation

MCMM timing analysis

Parasitic extraction

LEC

Formal/LEC tools

Implementation tools

I niti advisors?

Scripting fundamentals

Education

BE/BTech/MTech in Electronics or Electrical Eng

Tools

Innovus

ICC2

Fusion Compiler

StarRC

Formal/Location?

Job description

Job Requirements

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Role Overview

Drive full-chip or subsystem static timing analysis and timing closure across multiple modes and corners. The role needs strong constraint understanding, path-level debugging, timing-model awareness and the ability to translate analysis into implementable ECO actions.

Key Responsibilities

• Perform STA and timing signoff using PrimeTime and/or Tempus


• Validate SDC constraints, clocks, generated clocks, exceptions, IO delays and mode/corner coverage


• Analyse setup, hold, recovery/removal, clock-gating and other relevant timing checks


• Debug interface timing, block-to-block paths, clock interactions and constraint-quality issues


• Build, validate and use timing models for hierarchical analysis where applicable


• Analyse OCV/AOCV/POCV, SI/crosstalk and parasitic effects on timing convergence


• Generate timing ECO recommendations and work with PnR/implementation teams through closure


• Support LEC, extraction correlation, QoR reporting and signoff review readiness


• Collaborate with RTL, synthesis, PnR, DFT and methodology teams to resolve root causes

Required Skills & Expertise

• 5-10 years of relevant STA/timing closure experience at subsystem or full-chip level


• Strong hands‑on expertise in PrimeTime and/or Tempus


• Strong SDC knowledge and experience debugging incorrect, incomplete or conflicting constraints


• Experience with MCMM timing analysis, path-based debugging and timing ECO generation


• Understanding of parasitic extraction using StarRC or equivalent


• Working knowledge of LEC using Formality or equivalent


• Exposure to implementation tools such as Innovus, ICC2 or Fusion Compiler for timing correlation


• Ability to communicate timing risks and closure actions clearly to implementation and design teams

Preferred Skills

• TCL scripting capability; Python is an advantage


• Familiarity with hierarchical timing models and interface closure


• Exposure to advanced-node timing effects without requiring proprietary programme details

Education

BE/BTech/MTech in Electronics, Electrical Engineering or a related discipline.

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.