Technical Lead

Quest Global; Bengaluru; On-site; INR 1,400,000 - 2,100,000; Full time

Job summary

Quest Global in Bengaluru is seeking a senior professional to lead end-to-end tile/block physical design from handoff to signoff-ready delivery. You will own floorplan feasibility, power planning, placement, CTS, routing and post-route optimization with a strong emphasis on timing closure and PPA.

You will mentor engineers and drive multi‑mode timing convergence across RTL, synthesis, STA, and full-chip teams.

Qualifications

• 10-12 years of ASIC physical design experience with tile/block ownership
• Hands-on experience with floorplanning, power planning, CT S, placement, routing and physical optimisation
• Timing convergence using PrimeTime/Tempus and ECO implementation
• Parasitic extraction with StarRC or equivalent and LEC with Formality or equivalent
• Ability to debug timing, congestion, clock, SI and physical implementation issues
• Experience leading engineers and delivering blocks against schedule and quality milestones
• Exposure to IR-drop/EM analysis and physical verification flows is a plus

Responsibilities

• Own floorplan feasibility, power planning, placement, clock-tree synthesis, routing and post-route optimisation
• Drive multi-mode, multi-corner timing convergence and PPA closure
• Review congestion, utilisation, clock quality, signal integrity and routability risks; define recovery actions
• Guide setup/hold, DRC, electrical, noise and design-rule ECO closure
• Ensure extraction, STA, LEC, physical-verification and power-integrity readiness for final handoff
• Lead technical reviews, daily closure tracking, dependency management and issue escalation
• Mentor tile owners and establish reusable checklists, scripts and best practices
• Coordinate interface assumptions and deliverables with RTL, synthesis, STA, DFT and full-chip teams

Skills

Tile/block ownership

Floorplanning

Power distribution

CTS routing optimization

PRIMETIME/TEMpUS timing closure

Debug complex timing

Leadership of engineers

Education

BE/BTech/MTech in Electronics or Electrical Engineering

Tools

Cadence Innovus

Synopsys ICC2

Fusion Compiler

StarRC

Formality

Calibre

Pegasus

TCL scripting

Python

Job description

Job Requirements

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Role Overview

Lead end-to-end tile/block physical design execution from design handoff through signoff-ready delivery. The role requires recent hands-on closure experience, strong technical ownership, and demonstrated leadership of engineers working on complex, timing‑critical designs.

Key Responsibilities

• Own floorplan feasibility, power planning, placement, clock-tree synthesis, routing and post-route optimisation
• Drive multi-mode, multi-corner timing convergence and PPA closure
• Review congestion, utilisation, clock quality, signal-integrity and routability risks; define recovery actions
• Guide setup/hold, DRC, electrical, noise and design‑rule ECO closure
• Ensure extraction, STA, LEC, physical‑verification and power‑integrity readiness for final handoff
• Lead technical reviews, daily closure tracking, dependency management and issue escalation
• Mentor tile owners and establish reusable checklists, scripts and best practices
• Coordinate interface assumptions and deliverables with RTL, synthesis, STA, DFT and full‑chip teams

Required Skills & Expertise

• 10-12 years of relevant ASIC physical design experience, including recent tile/block ownership
• Strong hands‑on experience with Cadence Innovus and/or Synopsys ICC2 / Fusion Compiler
• Strong understanding of floorplanning, power distribution, placement, CTS, routing and physical optimisation
• Timing closure experience using PrimeTime and/or Tempus, including MCMM analysis and ECO implementation
• Working knowledge of parasitic extraction using StarRC or equivalent and LEC using Formality or equivalent
• Ability to debug complex timing, congestion, clock, SI and physical implementation issues
• Experience leading engineers and delivering blocks against schedule and quality milestones

Preferred Skills

• Exposure to IR-drop/EM analysis using RedHawk or Voltus
• Familiarity with Calibre/Pegasus‑class physical verification flows
• Strong TCL scripting; Python is an advantage
• Experience on advanced-node designs without requiring disclosure of proprietary project details

Education

BE/BTech/MTech in Electronics, Electrical Engineering or a related discipline.

Company Culture

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference‑makers in our workplace.