Senior EMIR Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru is seeking an EMIR Engineer to drive power integrity, IR drop, and electromigration analysis for advanced SoC designs. The role requires leading EMIR sign-off methodology, PDN planning, and chip-package co-design while mentoring a team of engineers.

Experience required is 3 to 6 years, with hands-on work across verification, design convergence, and collaboration with RTL, PD, and packaging teams.

Qualifications

• 3–6 years of experience in EMIR analysis and power integrity.
• Strong knowledge of EMIR sign-off methodology and PDN planning.
• Ability to lead and mentor a team of engineers.

Responsibilities

• Lead IR drop, electromigration, and power integrity analysis across blocks and full-chip designs.
• Define, implement, and optimize EMIR sign-off flows using industry tools (Redhawk, Voltus, Totem).
• Drive PDN architecture planning with PD and Physical Design teams.
• Perform chip-package co-simulation to validate power distribution across die, package, and board.
• Review EMIR reports, debug issues, and provide closure recommendations.
• Own and automate EMIR flows using scripting (Python/Perl/TCL).
• Mentor junior engineers in EMIR methodologies and best practices.

Skills

Power integrity

IR drop

Electromigration

EMIR sign-off

PDN planning

Tools

Redhawk

Voltus

Totem

Job description

Role Overview:

We are seeking a EMIR Engineer to drive power integrity, IR drop, and electromigration analysis for advanced SoC designs. The ideal candidate will have strong expertise in EMIR sign-off methodology, PDN planning, and chip-package co-design, along with the ability to lead and mentor a team of engineers.

Experience :- 3 Years to 6 Years

Key Responsibilities:

• Lead IR drop, electromigration, and power integrity analysis across multiple blocks and full-chip designs.
• Define, implement, and optimize EMIR sign-off flows using industry-standard tools (Redhawk, Voltus, Totem, etc.).
• Drive PDN architecture planning and collaborate with Physical Design teams to ensure robust power delivery.
• Perform chip-package co-simulation to validate power distribution across die, package, and board.
• Review and analyze EMIR reports, debug issues, and provide recommendations to closure.
• Own and automate EMIR flows using Python/Perl/TCL scripting.
• Collaborate with cross-functional teams (RTL, PD, Verification, Packaging) for design convergence.
• Mentor and guide junior engineers in EMIR methodologies and best practices.