Senior Director DFT Bengaluru

JobCrexa; India; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Eximietas Design in Visakhapatnam, India, seeks a Senior Director of Design for Test (DFT) to lead end-to-end DFT flows from RTL to sign-off across complex IP, subsystems, and SoCs.

The role requires deep expertise in ATPG, DRC, MBIST, and JTAG/IJTAG implementations, with hands-on experience in Tessent, TestMAX/TetraMAX, or Modus alongside scripting in TCL, Python, or Perl. Collaborative cross-team leadership is essential.

Qualifications

• End-to-end ownership of the DFT flow from RTL to sign-off.
• Experience with scan architecture, EDT & OCC.
• ATPG, DRC analysis, coverage optimization, and pattern simulations.
• SoC integration with pattern retargeting and DFT debugging.
• MBIST, IJTAG and boundary-scan (JTAG) integration.
• DFT sign-off ownership and deliverables.
• Hands-on with Tessent, TestMAX/TetraMAX, or Modus.

Responsibilities

• End-to-end ownership of DFT implementation flow from RTL to sign-off.
• Scan architecture implementation including EDT & OCC.
• ATPG, DRC analysis, coverage optimization, and pattern simulations.
• SoC integration, pattern retargeting, and DFT debugging.
• MBIST, IJTAG, and boundary-scan integration.
• Collaborate with Design, Verification, and Physical Design teams.
• DFT sign-off ownership and deliverables.

Skills

End-to-End DFT

Scan Insertion

ATPG & DRC

Pattern Debugging

SoC Pattern Retargeting

DFT Sign-off

JTAG & IJTAG

Tools

Tessent

TestMAX/TetraMAX

Cadence Modus

Job description

Hi All, Greetings from Eximietas Design! We're Hiring | Senior Director DFT | Eximietas Design

Locations

• India: Bengaluru, Hyderabad, Ahmedabad & Visakhapatnam.
• San Jose (Bay Area), USA

Eligibility (USA)

U.S. Permanent Residents (Green Card holders).

Experience

25 Years.

Job Description

We are seeking motivated Design for Test (DFT) professionals to join our growing team. You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across complex IP, Subsystem, and SoC designs.

Key Skills

• End-to-End DFT Flow Ownership.
• Scan Insertion, EDT & OCC.
• ATPG, DRC Analysis & Coverage Closure.
• Pattern Simulation & Debugging.
• SoC Integration & Pattern Retargeting.
• MBIST, IJTAG & JTAG Implementation.
• DFT Sign-off Activities.

Tools Expertise

• Siemens Tessent.
• Synopsys TestMAX / TetraMAX.
• Cadence Modus.

Preferred Skills

• Streaming Scan Network (SSN).
• Analog & Mixed-Signal DFT.
• SpyGlass DFT.
• RTL DFT Methodologies.
• TCL, Python & Perl Scripting.

Core Responsibilities

• End-to-end ownership of DFT implementation flow from RTL to sign-off.
• Scan architecture implementation including EDT & OCC.
• ATPG, DRC analysis, coverage optimization, and pattern simulations.
• SoC integration, pattern retargeting, and DFT debugging.
• MBIST, IJTAG, and Boundary Scan (JTAG) integration.
• Collaboration with Design, Verification, and Physical Design teams.
• DFT sign-off ownership and deliverables.

Technical Requirements

• Strong experience in ATPG simulations and netlist handling.
• Expertise in block-level and SoC-level pattern retargeting/debugging.
• Strong understanding of ICL and PDL standards.
• Hands-on experience with Tessent, TestMAX/TetraMAX, or Modus.

Contact

Maruthy Prasaad Associate VLSI Manager Talent Acquisition | Visakhapatnam Eximietas Design ( Excellence by Design) Inspired by nature, driven by silicon. .