Senior DFT Engineer

Qualcomm; Dadri; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Qualcomm India Private Limited is seeking an ASIC Engineer to define, model, design (digital and/or analog), and optimize IP/SoC development. You will verify, validate, and document IP while collaborating with cross-functional teams across an international, dynamic environment.

The role requires strong DFT knowledge, experience with ATPG, scan insertion, and scripting. Excellent communication in English is essential for teamwork and project execution.

Qualifications

• Bachelor's degree with 2+ years ASIC-related experience.
• Master's degree with 1+ year ASIC-related experience.
• PhD in Science, Engineering, or related field.
• Strong knowledge of DFT concepts and test methodologies.

Responsibilities

• Define, model, and design IP/SoC (digital and/or analog).
• Optimize, verify, and validate IP implementations.
• Document IP development and collaborate with cross-functional teams.
• Work in an international, dynamic environment and multi-task across high-priority designs.

Skills

ASIC design

DFT concepts

ATPG / scan insertion

Scripting (Perl, Shell)

Test vector simulation

English communication

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

SpyGlass RTL lint

TK (Test Knowledge)

TetraMax / DFTMax

Cadence Encounter Test

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications:

• • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• • Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• • PhD in Science, Engineering, or related field.
• • 3+ years experience in the area of ASIC/DFT
  • - In depth knowledge of DFT concepts
  • - In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis
  • - Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations
  • - Expertise in scripting languages such as perl, shell, etc.
  • - Experience in simulating test vectors
  • - Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax)
  • - Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus
  • - Ability to work in an international team, dynamic environment
  • - Ability to learn and adapt to new tools and methodologies.
  • - Ability to do multi-tasking & work on several high priority designs in parallel.
  • - Excellent problem solving skills
  • - Excellent communication and team work skills and good English is required

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