Senior Engineer - DFT

Qualcomm; Bengaluru; On-site; INR 900,000 - 1,400,000; Full time

Job summary

Qualcomm India Private Limited is seeking a Hardware Engineer to plan, design, verify and test electronic systems including DFT/ASIC flows. You will work on scan insertion, ATPG, timing fixes, and test vector simulations across RTL and physical stages, in a globally distributed team.

Required: 3–4+ years in hardware engineering, strong knowledge of DFT concepts, and scripting skills in Perl or Shell. Collaborative problem solving and excellent communication are essential.

Qualifications

• Bachelor’s degree with 4+ years hardware engineering experience.
• Master’s with 3+ years hardware experience.
• PhD with 2+ years hardware experience.

Responsibilities

• ASIC/DFT design and verification tasks.
• DFT concepts, scan insertion and ATPG.
• Time-timing fixes for violations and test constraints.
• Scripting for automation (Perl, Shell).
• Simulate test vectors and ensure RTL/DFT quality.
• Work across RTL, gate-level, and test benches in a global team.

Skills

ASIC/DFT experience

DFT concepts

Scripting (Perl, Shell)

Test vector simulation

Multi-tasking in parallel designs

Education

Bachelor's degree in CS/EE/Engineering

Master's degree in CS/EE/Engineering

PhD in CS/EE/Engineering

Tools

Genus

Synopsys TetraMax/DFTMax

Cadence Encounter Test

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Description

• Minimum of 3+ years experience in the area of ASIC/DFT
• In depth knowledge of DFT concepts
• In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis
• Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations
• Expertise in scripting languages such as perl, shell, etc.
• Experience in simulating test vectors
• Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (Tessent, TK, TetraMax)
• Working experience in Genus, Synopsys TetraMax/DFTMax and Cadence Encounter Test is a plus
• Ability to work in an international team, dynamic environment
• Ability to learn and adapt to new tools and methodologies.
• Ability to do multi-tasking & work on several high priority designs in parallel.
• Excellent problem solving skills
• Excellent communication and team work skills and good English is require

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