Senior STA Engineer

QUALCOMM, Inc.; Dadri; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Qualcomm India Private Limited is seeking an ASIC Engineer to define, model and design IP/SoC blocks for high performance, low‑power products. You will verify and validate implementations, optimize timing and power, and document development flows to ensure quality results.

Join a collaborative team that works with cross‑functional groups to drive PPA improvements, ECOs and complex timing convergence across corners and process nodes.

Qualifications

• Bachelor's or higher in science or engineering with ASIC work experience.
• Masters or PhD preferred for advanced roles in design and verification.
• Experience in physical implementation and timing/convergence.

Responsibilities

• Define, model, design and optimize IP/SoC blocks for high performance ASICs.
• Verify, validate and document ASIC design flows and ECOs for timing.
• Collaborate with cross‑functional teams to drive PPA improvements.

Skills

Perl

TCL language

STA knowledge

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

PT

Tempus

GENUS

Innovus

ICC

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• OR
• PhD in Science, Engineering, or related field.

Desired experience:

• 3+ years of experience in static timing analysis, constraints and other physical implementation aspects.
• Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc.
• Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths.
• Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs.
• Should be aware about the tricks for minimizing power.
• Experience in deep submicron process technology nodes is strongly preferred.
• Knowledge of high performance and low power implementation methods is preferred.
• Willing to push PPA to the best possible extent.
• Strong fundamentals.
• Expertise in Perl, TCL language

Applicants:

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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