Senior Design Verification Engineer - Kochi

N Human Resources & Management Systems; Ernakulam; On-site; INR 2,800,000 - 4,000,000; Full time

Job summary

N Human Resources & Management Systems is hiring a Senior Design Verification Engineer in Kerala, India. You will own functional verification for design blocks and subsystems, build verification environments, and drive coverage closure to silicon-quality tapeout readiness.

Responsibilities include developing UVM-based testbenches, writing test plans, and guiding a small team of 3-4 engineers. You will collaborate with design, DFT, and architecture teams to shape verification strategy and sign

Qualifications

• 5+ years of hands-on experience in functional verification using UVM/SystemVerilog.
• Strong understanding of coverage-driven verification methodology.
• Experience with simulation, debug, and regression tools (VCS/Questa or equivalent).

Responsibilities

• Develop and maintain UVM-based verification environments and testbenches.
• Write test plans, directed and constrained-random tests, and functional/code coverage models.
• Debug RTL and testbench issues, and drive bugs to closure with design teams.
• Perform assertion-based verification (SVA) and formal verification where applicable.
• Lead and mentor a team of 3-4 verification engineers.
• Own verification signoff and regression health for assigned blocks.
• Collaborate with design, DFT, and architecture teams on verification strategy.

Skills

UVM / SystemVerilog

Coverage-driven verification

VCS / Questa

Tools

VCS

Questa

Job description

N Human Resources & Management Systems | Full time

We are hiring a Senior Design Verification Engineer to own functional verification for design blocks and subsystems. You will build and maintain verification environments, drive coverage closure, and ensure silicon-quality signoff before tapeout.

Key Responsibilities:

• Develop and maintain UVM-based verification environments and testbenches
• Write test plans, directed and constrained-random tests, and functional/code coverage models
• Debug RTL and testbench issues, and drive bugs to closure with design teams
• Perform assertion-based verification (SVA) and formal verification where applicable
• Lead and mentor a team of 3-4 verification engineers
• Own verification signoff and regression health for assigned blocks
• Collaborate with design, DFT, and architecture teams on verification strategy

Requirements:

• 5+ years of hands-on experience in functional verification using UVM/SystemVerilog
• Strong understanding of coverage-driven verification methodology
• Experience with simulation, debug, and regression tools (VCS/Questa or equivalent)