Senior Design Verification Engineer - Kochi

n Human Resources & Management Systems [ nHRMS ]; Ernakulam; On-site; INR 2,500,000 - 4,200,000; Full time

Job summary

nHRMS is seeking a Senior Design Verification Engineer in India to own functional verification for design blocks and subsystems. You will build and maintain verification environments, drive coverage closure, and ensure silicon-quality signoff before tapeout.

You will develop UVM-based testbenches, write test plans, and implement directed and constrained-random tests with coverage models. You will lead a small team and collaborate closely with design and architecture groups to define verification

Qualifications

• 5+ years of hands-on verification experience using UVM/SystemVerilog.
• Strong knowledge of coverage-driven verification methodologies.

Responsibilities

• Develop and maintain UVM-based verification environments and testbenches (CW/CR tests).
• Write test plans, directed and constrained-random tests, and coverage models.
• Debug RTL and testbench issues; drive bugs to closure with design teams.
• Perform assertion-based verification (SVA) and formal verification where applicable.
• Lead and mentor a team of 3–4 verification engineers.
• Own verification signoff and regression health for assigned blocks.
• Collaborate with design, DFT, and architecture teams on verification strategy.

Skills

UVM

SystemVerilog

Coverage-driven verification

Assertion-based verification

Formal verification

Tools

VCS

Questa

Job description

Job Description:

We are hiring a Senior Design Verification Engineer to own functional verification for design blocks and subsystems. You will build and maintain verification environments, drive coverage closure, and ensure silicon-quality signoff before tapeout.

Key Responsibilities:

• Develop and maintain UVM-based verification environments and testbenches
• Write test plans, directed and constrained-random tests, and functional/code coverage models
• Debug RTL and testbench issues, and drive bugs to closure with design teams
• Perform assertion-based verification (SVA) and formal verification where applicable
• Lead and mentor a team of 3-4 verification engineers
• Own verification signoff and regression health for assigned blocks
• Collaborate with design, DFT, and architecture teams on verification strategy

Requirements:

• 5+ years of hands-on experience in functional verification using UVM/SystemVerilog
• Strong understanding of coverage-driven verification methodology
• Experience with simulation, debug, and regression tools (VCS/Questa or equivalent)