Senior Design Verification Engineer

eInfochips (An Arrow Company); Bengaluru; On-site; INR 1,000,000 - 2,000,000; Full time

Job summary

A semiconductor manufacturing company in Bengaluru is seeking an experienced Associate Manager in Talent Acquisition. Ideal candidates should have extensive expertise in development and verification processes, particularly within the VLSI domain. Responsibilities include executing compliance projects, mentoring teams, and engaging in client communications. Candidates with at least 4 years in SystemVerilog and relevant SoC project experience are encouraged to apply.

Qualifications

• At least 4 years of experience in SystemVerilog HVL.
• Hands-on experience developing assertions and coverage plans.
• Must have executed at least 1 SoC verification project.

Responsibilities

• Develop UVM-based SV test-benches to ensure compliance with specifications.
• Execute complete verification projects with hands-on experience and client interactions.
• Mentor junior engineers through technical reviews.

Skills

UVM-based SV test-benches

Defining test plans

Verification methodologies

Development of assertions and checkers

Experience in PCIe, NVMe, NAND

Education

B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering

Job description

Overview

Associate Manager- Talent Acquisition at eInfochips Pvt. Ltd. Experienced Recruitment Professional | VLSI Industry Specialist | Talent Acquisition…

Responsibilities

• An expert level with developing UVM-based SV test-benches.
• Highly experienced with defining block, sub-system and SOC top level test plans.
• Relevant experience with one or more of PCIe, NVMe, NAND, DDR and CPU sub-systems.
• Deep understanding and knowledge of verification methodologies, flows and quality metrics.
• The incumbent will be responsible for executing complete verification projects with hands-on experience, mentoring, client communication/interactions, in-depth technical reviews, and close tracking of technical as well as management aspects.

Essential Skills & Experience

• At least 4 years of experience in SystemVerilog HVL.
• At least 3 years of experience in OVM/UVM/VMM/Test Harness.
• Hands-on experience developing assertions, checkers, coverage and scenario creation.
• Must have executed at least 1 SoC verification project.
• Experience in developing test and coverage plans, verification environments and validation plans.
• Knowledge of at least one industry-standard protocol such as Ethernet, PCIe, MIPI, USB, or similar.

Education Background

B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.

Seniority level

• Associate

Employment type

• Full-time

Industries

• Semiconductor Manufacturing