Senior Analog Design Engineer

Tata Consultancy Services; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

Tata Consultancy Services is looking for a Senior Analog Design Engineer specializing in Memory Cell Design in Bengaluru, India. The ideal candidate will possess expertise in full-custom analog design, particularly in advanced-node technologies. Responsibilities include designing memory bit-cells, PLL circuits, and collaborating closely with layout teams. A B.Tech or M.Tech in VLSI/Microelectronics and 5-10 years of experience in custom analog design are required. Familiarity with industry-standard EDA tools is essential, and scripting knowledge is an advantage.

Qualifications

• 5 to 10 years of strong experience in custom analog / mixed-signal IC design in sub 2nm technology nodes.
• Expertise in advanced-node analog and mixed-signal circuit design.
• Scripting knowledge (Skill / Python / Perl / TCL) is a plus.

Responsibilities

• Design and optimize memory bit-cells in sub-2nm / Angstrom-class process nodes.
• Develop high-performance PLL / DLL / clock-generation circuits.
• Design transistor-level analog circuits in advanced FinFET / GAA technologies.
• Collaborate with layout teams to ensure design closure.

Skills

Advanced-node analog design

Memory cell design

Mixed-signal circuit design

Transistor-level design

Custom analog design

Education

B.Tech / M.Tech in VLSI / Microelectronics

Tools

Cadence EDA tools

Synopsis EDA tools

Siemens EDA tools

Job description

Job Title: Senior Analog Design Engineer specialized in Memory Cell Design

Job Summary

Analog Design Engineer with strong expertise in advanced-node analog and mixed-signal circuit design, specifically in memory bit-cell/periphery design at Angstrom-class technology nodes and PLL / clock-generation architectures.

The role involves transistor-level design, simulation, and optimization of high-performance analog circuits for next-generation SoCs, memory interfaces, and compute platforms.

The ideal candidate will have deep experience in custom analog design, device-level circuit optimization, PPA tradeoffs, and design closure in deeply scaled technologies, with exposure to FinFET / GAA -era design challenges.

Key Responsibilities

1. Memory Cell Design (Angstrom Nodes)

   Design and optimize memory bit-cells (e.g., SRAM / register-file / custom embedded memory cells) in sub-2nm / Angstrom-class process nodes.

   Perform read/write stability analysis including SNM (Static Noise Margin), Write margin, Read disturb, Leakage analysis,, Variability / mismatch sensitivity.

   Optimize memory circuits for Low voltage operation, High-speed access, Leakage reduction, Reliability and yield, Drive Monte Carlo, PVT, aging, and mismatch simulations for robust design closure.

2. PLL / Clocking Circuit Design

   Desgn and develop high-performance PLL / DLL / clock-generation circuits for SoC and memory subsystems.

   Architect and implement Phase/Frequency Detectors (PFD), Charge Pumps, Loop Filters, Voltage-Controlled Oscillators (VCO), Ring / LC oscillators, Frequency dividers, Clock buffers / distribution blocks.

   Perform loop stability, jitter, phase noise, spur, and lock-time optimization.

   Design PLLs for Low-jitter clocking, High-speed memory interfaces, On-chip clock synthesis.

   Analyze PLL behavior across PVT, noise, substrate coupling, and supply variations and Work with system teams for clock architecture integration and timing requirements.

3. Advanced Node Analog Design

   Design transistor-level analog circuits in advanced FinFET / GAA in Angstrom nodes.

   Address deep-submicron challenges including Reduced intrinsic gain, Device variability, Self-heating, Layout-dependent effects, Parasitic dominance.

   Perform full-custom analog design and simulation for Bias circuits, Bandgap References, Regulators, Data-path analog blocks, Interface circuits

   Ensure robust design across reliability corners including EM/IR, Aging (BTI / HCI), ESD-aware interfaces, Thermal sensitivity

4. Layout Collaboration & Design Closure

   Work closely with layout teams on Floor planning, Matching-sensitive placement, Parasitic-aware optimization, DFM / yield-aware layout practices.

Required Qualifications

• B.Tech / M.Tech in VLSI / Microelectronics.
• 5 to 10 years of strong experience in custom analog / mixed-signal IC design in sub 2nm technology nodes.
• Tools & Methodologies – Expertise on industry sign-off EDA tool suites from Cadence, Synopsis and Siemens.

Good to have

• Experience with custom high-speed clocking for SerDes / DDR / LPDDR.
• Scripting knowledge (Skill / Python / Perl / TCL).