Senior Analog Design Engineer

eInfochips (An Arrow Company); Bengaluru; On-site; INR 3,000,000 - 5,500,000; Full time

Job summary

eInfochips (An Arrow Company) is seeking an experienced analog/mixed-signal designer with 5–10 years of exposure to RFIC blocks such as PLLs, LNA, and mixers. The role requires hands-on experience with planar to FinFET transition, pre/post-layout verification, and scripting in Python or TCL to automate design flows.

Proficiency in Cadence Virtuoso, Spectre, HSPICE, and reliability/verification tools is essential.

Qualifications

• 5–10 years of analog/mixed-signal design experience.
• Experience with RFIC blocks including PLLs, ADCs/DACs, LNA.
• Proficient in pre-layout and post-layout verification and statistical analysis.

Responsibilities

• Design and optimize analog/mixed-signal blocks across process nodes.
• Perform pre-layout and post-layout simulations with Monte Carlo and corner analysis.
• Translate designs from Planar (e.g., 28nm) to FinFET nodes.
• Drive design methodologies and automation using Python/SKILL/Tcl.

Skills

Analog design

RFIC design

PLL design

LNA design

Mixer design

Python scripting

SKILL

Tcl

Tools

Cadence Virtuoso

Spectre

HSPICE

CustomSim

Mentor Calibre

Synopsys IC Validator

Voltus

RedHawk

Job description

Principal Accountabilities

• Analog designer with experience of 5 to 10 Years of experience in below,
• CT sigma delta ADC, RFIC design: LNA and mixer, PLLs
• Circuit Architecture & Design: Architect and design high-performance analog/mixed-signal building blocks (e.g., PLLs, ADCs/DACs, RFIC).
• EDA exposure: Custom Design/Schematic: Cadence Virtuoso (ADE/Maestro). Simulation: Spectre, HSPICE, or CustomSim. Physical Verification: Mentor Calibre (DRC/LVS/PEX) or Synopsys IC Validator. Reliability/Sign-off: Experience with Voltus, RedHawk, or similar power/IR integrity tools
• Multi-Node Design: Translate and optimize designs across different process geometries, including transition strategies from Planar (e.g., 28nm) to FinFET (e.g., 16nm, 7nm…) nodes.
• Simulation & Verification: Perform comprehensive pre-layout and post-layout simulations, including Monte Carlo, corner analysis, noise analysis, and reliability modeling (EM/IR/Aging/BTI/HCI).
• Methodology: Drive best practices in analog design methodology, including the adoption of automated design tools and script-based verification (Python/SKILL/Tcl).