Analog Circuit Design Engineer

Silcosys Solutions; Dadri, Hyderabad, Bengaluru; On-site; INR 3,000,000 - 5,400,000; Full time

Job summary

Silcosys Solutions seeks a Senior Analog Design Engineer with 6+ years of hands-on experience in analog and mixed-signal IC design. You will drive the full design flow from spec to silicon validation, collaborating with layout, digital, and validation teams.

Key responsibilities include designing IPs (ADCs, DACs, LDOs, Bandgaps, PLLs, Op-Amps), performing pre/post-layout simulations, and leading block-level reviews and documentation. Strong leadership and communication skills required.

Qualifications

• 6+ years of hands-on analog IC design in CMOS processes.
• Strong fundamentals and trade-off analysis in analog design.
• Experience with simulation tools: Spectre, HSPICE, Monte Carlo.
• Proven tape-out and silicon validation success.

Responsibilities

• Design and develop analog/mixed-signal IPs such as ADCs, DACs, LDOs, Bandgaps, PLLs, Op-Amps.
• Perform schematic entry, simulations (pre-layout/post-layout), and layout supervision.
• Drive transistor-level design using industry-standard tools (Cadence/Synopsys).
• Lead block-level design reviews, documentation, and verification.
• Collaborate with layout, digital, and validation teams across the project lifecycle.
• Support silicon bring-up, debug, and characterization.

Skills

Analog IC Design

CMOS Processes

Cadence/Synopsys

Schematic & Layout supervision

Tape-out & silicon validation

Tools

Cadence

Synopsys

Spectre/HSPICE

Job description

We are seeking a highly skilled Senior Analog Design Engineer with 6+ years of experience in designing, simulating, and validating analog and mixed-signal circuits. The ideal candidate should have hands‑on expertise across the full custom design flow, from specification to silicon validation.

Key Responsibilities

• Design and develop analog/mixed-signal IPs such as ADCs, DACs, LDOs, Bandgaps, PLLs, Op-Amps, etc.
• Perform schematic entry, simulations (pre-layout/post-layout), and layout supervision.
• Drive transistor-level design using industry-standard tools (Cadence/Synopsys).
• Lead block-level design reviews, documentation, and verification.
• Collaborate with layout, digital, and validation teams across the project lifecycle.
• Support silicon bring-up, debug, and characterization.

Requirements

• 6+ years of hands‑on analog IC design experience in CMOS processes (28nm/65nm/180nm, etc.)
• Strong knowledge of analog fundamentals and design trade-offs.
• Experience with simulation tools like Spectre, HSPICE, and Monte Carlo analysis.
• Proven tape-out and silicon success experience.
• Good communication and team leadership skills.