Semiconductor Design Engineer 2 (BB35FT RM 4456)

Source-Right; Hyderabad; On-site; INR 900,000 - 1,200,000; Full time

Job summary

Source-Right is seeking a Semiconductor Design Engineer 2 to contribute to pre-silicon verification and analog/digital mixed-signal design. The role focuses on SV/UVM, Verilog, and CMOS concepts with hands-on use of Cadence tools in a collaborative environment.

The candidate should have at least 1 year of relevant experience, a Electronics degree, and strong debugging, regression, and waveform analysis skills to deliver robust IP and SoC verification.

Skills

Digital Circuits

Analog Circuits

SV/UVM

Verilog

CMOS Concepts

Pre-Silicon Verification

Gate Level Simulation

SystemVerilog Assertions

Debug

Regression

Waveform Analysis

Root Cause Analysis

Cadence Virtuoso

Spectre

Xcelium

AMS Designer

Synopsys VCS

UVM Testbench Development

Full-Chip Pre-Silicon Verification

DRAM Verification

Functional Coverage Closure

Python/Perl/Tcl Automation

Cross-Team Execution

Education

B.E./B.Tech in Electronics, M.Tech

Tools

Cadence Virtuoso

Spectre

Xcelium

AMS Designer

Synopsys VCS

Job description

Position: Semiconductor Design Engineer 2 (BB35FT RM 4456)

Minimum Qualification Required: B.E./B.Tech in Electronics, M.Tech

MSP Input – Supplier Inputs

• Candidate Skill: Digital/Analog Circuits, SV/UVM, Verilog, CMOS Concepts
• Years of Experience/Expectations: Minimum 1 Year
• Mandatory/Optional: Mandatory
• Candidate Skill: Pre-Silicon Verification, Gate Level Simulation (GLS), SystemVerilog Assertions
• Years of Experience/Expectations: Minimum 1 Year
• Mandatory/Optional: Mandatory
• Candidate Skill: Debug, Regression, Waveform Analysis, Root Cause Analysis
• Years of Experience/Expectations: Minimum 1 Year
• Mandatory/Optional: Mandatory
• Candidate Skill: Tools & Collaboration, Cadence Virtuoso, Spectre, Xcelium, AMS Designer, Synopsys VCS
• Years of Experience/Expectations: Minimum 1 Year
• Mandatory/Optional: Mandatory
• Candidate Skill: Strong SV/UVM, Functional Verification, UVM Testbench Development
• Years of Experience/Expectations: Minimum 1 Year
• Mandatory/Optional: Mandatory
• Candidate Skill: Hands-on SoC/Full-Chip Pre-Silicon Verification, DRAM Verification
• Years of Experience/Expectations: Minimum 1 Year
• Mandatory/Optional: Mandatory
• Candidate Skill: Proven Debug Depth, Regression Optimization, Functional Coverage Closure
• Years of Experience/Expectations: Minimum 1 Year
• Mandatory/Optional: Mandatory
• Candidate Skill: Comfortable with EDA Tools, Python/Perl/Tcl Automation, Cross-Team Execution
• Years of Experience/Expectations: Minimum 1 Year
• Mandatory/Optional: Mandatory