RTL Lead

Quest Global; Bengaluru; On-site; INR 2,000,000 - 3,800,000; Full time

Job summary

Quest Global in Bengaluru seeks a senior digital design engineer to drive microarchitecture and RTL feature development for processor platforms.

You will lead a team of engineers, oversee timing and synthesis, and optimize power, performance, and area while collaborating with architecture, verification, and physical design groups.

Qualifications

• Hands-on experience in RTL design and microarchitecture.
• Experience leading digital design teams and mentoring engineers.
• Strong knowledge of ARM or RISC-V architectures.
• Familiar with bus protocols (AXI/AHB) and high-speed interfaces (PCIe/USB/DDR).
• Experience with sign-off methodologies and debugging complex issues.

Responsibilities

• Design and implement microarchitecture/RTL features for processors and platform products.
• Manage, mentor, and set goals for a team of digital engineers involved in design, synthesis, and timing.
• Oversee design reviews to optimize Power, Performance, and Area (PPA) metrics.
• Partner with architecture, verification, and physical design teams.
• Drive resolution on complex bugs, logic issues, and sign-off checks.
• Familiarity with ARM or RISC-V processors, bus protocols (AXI/AHB), and high-speed interfaces (PCIe, USB, DDR).
• Experience with Static Timing Analysis (STA), Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC).

Skills

Microarchitecture

RTL design

Team leadership

PPA optimization

Cross-functional

Sign-off debugging

ARM/RISC-V

AXI/AHB

PCIe/USB

STA

CDC

LEC

Tools

STA

CDC

LEC

Job description

• Design and Implementation: Design and implement microarchitecture/RTL features for processors and platform products.
• Team Leadership: Manage, mentor, and set goals for a team of digital engineers involved in design, synthesis, and timing.
• PPA Optimization: Oversee design reviews to optimize Power, Performance, and Area (PPA) metrics.
• Cross-Functional Collaboration: Partner with architecture, verification, and physical design teams.
• Sign-off & Debug: Drive resolution on complex bugs, logic issues, and sign-off checks.
• Architecture Knowledge: Familiarity with ARM or RISC-V processors, bus protocols (AXI/AHB), and high-speed interfaces (PCIe, USB, DDR).
• Sign-off Methodologies: Experience with Static Timing Analysis (STA), Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC).