FPGA/RTL Design Engineer

SEMI LEAF; Hyderabad; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

SEMI LEAF is looking for an FPGA RTL Design Engineer in Hyderabad, India. The role involves FPGA-based digital design, RTL development, and verification support for high-performance applications.

The ideal candidate should possess strong skills in RTL design with Verilog/SystemVerilog, FPGA development flows, and high-speed interfaces. Preferred qualifications include experience with hardware debugging tools and familiarity with embedded processors.

Qualifications

• 5 to 8 years of experience in FPGA design and development.
• Strong understanding of FPGA architectures and debugging.
• Experience with ASIC/SoC design prototyping is a plus.

Responsibilities

• Responsible for FPGA-based digital design and RTL development.
• Support verification, synthesis, and timing closure activities.
• Engage in FPGA bring-up activities for networking and communication applications.

Skills

RTL design using Verilog/SystemVerilog

Digital design fundamentals

FPGA development flows

High-speed interfaces (PCIe, DDR3/4/5)

Timing constraints and closure

Tools

AMD Vivado Design Suite

Intel Quartus Prime

Simulation tools (QuestaSim, Tcl, Python, Perl)

Job description

Job Title: FPGA RTL Design Engineer

We are seeking a talented FPGA RTL Design Engineer to join our hardware design team in Hyderabad.

• Location: Hyderabad, India
• Experience: 5 to 8 Years
• Employment Type: Full-Time

Job Summary

The ideal candidate will be responsible for FPGA-based digital design, RTL development, verification support, synthesis, timing closure, and FPGA bring‑up activities for high‑performance networking, communication, storage, or SoC‑based applications.

Required Skills

• Strong experience in RTL design using Verilog/SystemVerilog.
• Solid understanding of digital design fundamentals and computer architecture.
• Experience with FPGA development flows from RTL to bitstream generation.

Hands‑on Experience With FPGA Families

• AMD (Xilinx UltraScale)
• Intel

Experience With High‑speed Interfaces Such As

• PCIe
• DDR3 / DDR4 / DDR5
• Ethernet (1G/10G/25G/100G)
• AXI / AHB / APB protocols

Strong Understanding Of

• CDC / RDC analysis
• Timing constraints and timing closure
• FPGA resource optimization
• Reset and clocking architectures

Experience Using Simulation And Debug Tools. Tools & Technologies

• AMD Vivado Design Suite
• AMD Vitis Platform
• Intel Quartus Prime

Simulation Tools

• Siemens EDA QuestaSim
• Synopsys Tcl
• Python
• Perl

Preferred Qualifications

• Experience with FPGA prototyping of ASIC/SoC designs.
• Knowledge of DSP, signal processing, networking, or storage protocols.
• Experience with HLS (High‑Level Synthesis) methodologies.
• Familiarity with UVM-based verification environments.
• Exposure to embedded processors such as ARM-based FPGA SoCs.
• Experience with hardware debugging tools such as ILA, SignalTap, and protocol analyzers.