Application Specific Integrated Circuit Design Engineer

ACL Digital; Hyderabad; On-site; INR 600,000 - 1,000,000; Full time

Job summary

Join an innovative semiconductor manufacturing firm as an ASIC Design Engineer, where you'll play a critical role in ensuring the quality and efficiency of cutting-edge designs. This position offers the opportunity to work with advanced technology nodes and contribute to the development of high-performance ASICs. You will be responsible for setting up QA flows, running essential design checks, and collaborating with cross-functional teams to resolve complex design issues. If you are passionate about ASIC design and eager to make an impact in a dynamic environment, this role is the perfect fit for you.

Qualifications

• 3-5 years of experience in ASIC design and sub-20nm technology.
• Proficient in TCL, Perl, and Python scripting for automation.

Responsibilities

• Set up ASIC QA flows for RTL design quality checks.
• Run Lint, Synthesis, Static timing analysis, and other quality checks.
• Debug CDC and RDC issues while implementing RTL fixes.

Skills

ASIC Design Flow

TCL Scripting

Perl Scripting

Python Scripting

RTL Design Quality Checks

Static Timing Analysis

Debugging CDC/RDC Issues

Education

B.E/M.E/M.Tech in EE/CE

B.S/M.S in EE/CE

Tools

Lint

Synthesis

LEC

DFT

Job description

Application Specific Integrated Circuit Design Engineer

Direct message the job poster from ACL Digital

ASIC/SOC Front End Design Engineer

Responsibilities include:

1. Setting up ASIC QA flows for RTL design quality checks.
2. Understanding the design, including top-level interfaces, clock structure, reset structure, RAMs, CDC boundaries, and power domains.
3. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, and CLP steps.
4. Developing clock constraints, false paths, multi-cycle paths, IO delays, exceptions, and waivers.
5. Checking flow errors, design errors, violations, and reviewing reports.
6. Debugging CDC, RDC issues and implementing RTL fixes.
7. Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion, and DFT DRC & MBIST checks.
8. Handling multiple PNR blocks, building wrappers, and propagating constraints and waivers.
9. Porting flows or designs to different technology libraries.
10. Generating RAMs based on targeted memory compilers and integrating with RTL.
11. Running functional verification simulations as needed.

    Job Requirements:

    • B.E/M.E/M.Tech or B.S/M.S in EE/CE with 3 to 5 years of relevant experience.
    • Experience with ASIC design flow and direct experience in sub-20nm technology nodes.
    • Experience in signoff of front-end quality checks and metrics for various project milestones.
    • Proficiency in TCL, Perl, and Python scripting.

    Experience: 3 to 5 years

    Notice Period: Immediate

    Additional Details

    • Seniority level: Associate
    • Employment type: Full-time
    • Industry: Semiconductor Manufacturing

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