R&D Engineering, Sr Staff Engineer (RTL Design & Verification)

Grapevine Round1 AI; Bengaluru; On-site; INR 2,200,000 - 3,000,000; Full time

Job summary

Grapevine Round1 AI is seeking a Senior Staff Engineer for their Bengaluru office to lead RTL design and verification for Silicon Lifecycle Management and 3D-IC projects. This role involves developing test cases, debugging complex chip designs, and enhancing verification methodologies and automation flows.

The ideal candidate will have over 5 years of experience and strong expertise in System Verilog, Formal Verification, and EDA tools within a Unix/Linux environment, offering a high-impact contribution to next-generation semiconductor IP.

Qualifications

• 5+ years of hands-on experience in RTL design and verification.
• Proficiency in EDA tools.
• Experience with Formal Verification methodologies.

Responsibilities

• Lead RTL design and verification for Silicon Lifecycle Management and 3D-IC projects.
• Develop test cases and debug complex chip designs.
• Improve verification methodologies and automation flows.

Skills

RTL design

System Verilog

Formal Verification

EDA tools

Unix/Linux

TCL scripting

Job description

# R&D Engineering, Sr Staff Engineer (RTL Design & Verification)SynopsysBengaluru, Karnataka, IndiaPosted 20 Jun 2026Synopsys is seeking a Senior Staff Engineer for their Bengaluru office to lead RTL design and verification for Silicon Lifecycle Management (SLM) and 3D-IC projects. The role involves developing test cases, debugging complex chip designs, and improving verification methodologies and automation flows. Successful candidates will possess strong expertise in System Verilog, Formal Verification, and EDA tools within a Linux environment. The position offers high-impact work on next-generation semiconductor IP and opportunities for cross-functional collaboration.Matched by TALApply to this role now. Install TAL for a 24/7 AI agent that keeps finding roles personalised for you.Apply nowInstall TALExperience5+ yearsFunctionEngineeringWork modeOnsite, IndiaCompanyTier 1## What you will work onSynopsys is seeking a Senior Staff Engineer for their Bengaluru office to lead RTL design and verification for Silicon Lifecycle Management (SLM) and 3D-IC projects. The role involves developing test cases, debugging complex chip designs, and improving verification methodologies and automation flows. Successful candidates will possess strong expertise in System Verilog, Formal Verification, and EDA tools within a Linux environment. The position offers high-impact work on next-generation semiconductor IP and opportunities for cross-functional collaboration.## TAL's takeQuality 80/1005/5 clarityTier 1 companyHigh-caliber global semiconductor leader providing a specialized, high-impact staff engineering role in silicon lifecycle management.Very clear and specific requirements for RTL design and verification within the semiconductor domain.## Salaries at Synopsys23.3 LPA averageBased on 73 Grapevine salary entries for Synopsys.View all salariesEngineering0 - 2 years | L111 LPA averageRange: 6 - 14 LPAEngineering2 - 4 years | L218 LPA averageRange: 16 - 20 LPAEngineering4 - 6 years | L317 LPA averageRange: 7 - 24 LPAEngineering6 - 8 years | L329 LPA averageRange: 25 - 37 LPA## Must haves* 5+ years of hands-on experience in RTL design and verification* Proficiency in EDA tools* Expertise in Verilog and System Verilog* Experience with TCL scripting* Experience with Formal Verification methodologies* Proficiency in Unix/Linux environments## Tools and skillsverilogsystem verilogtclformal verification methodologieseda toolsunixlinuxNice to have: digital circuit design, analog circuit design, mixed-signal circuit design, 3d-ic standards.