Sr Staff Engineer, Formal Verification

Synopsys Inc; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Synopsys Inc. is seeking a Senior Staff Formal Verification Engineer to lead end-to-end formal verification for complex RTL designs in our Bangalore design center.

You will build and maintain verification flows, craft proofs, and mentor engineers to adopt formal methods across teams. You will collaborate with design and verification teams to identify critical corner cases, write strong assertions, and guide proofs to closure using tools like Jasper or VC-Formal.

Qualifications

• 8+ years in digital design or verification with at least 5 years in formal verification.
• Strong RTL, digital logic understanding and timing awareness.
• Proficient with Verilog or SystemVerilog; ability to read and debug RTL quickly.
• Experience with formal tools such as Jasper or VC-Formal; setup and debugging.
• Bachelor’s or Master’s in CS or EE; scripting skills are a plus.

Responsibilities

• Build and maintain end-to-end formal verification flow integrated into the broader verification process.
• Create formal verification plans and develop assertions, assumptions, and cover properties.
• Guide design and verification engineers in effective use of formal tools.
• Maintain and extend assertion libraries for both simulation and formal contexts.
• Apply techniques like bounded model checking, induction, and abstraction to prove RTL correctness.
• Debug RTL proofs, trace counterexamples to root cause, and mentor junior engineers.

Skills

Formal verification

RTL design

Debugging

Mentoring

Team collaboration

Education

Bachelor’s or Master’s in CS or Electrical Engineering

Tools

Jasper

VC-Formal

Verilog

SystemVerilog

Job description

Senior Staff Formal Verification Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent the better part of a decade proving that digital designs actually work, not just that they pass testbenches. Formal verification is where you live because you know that simulation can only show the presence of bugs, while formal methods can prove their absence. You have seen what happens when a corner case slips through, and you are the engineer who makes sure it does not.

You understand RTL at a level that lets you read a design and immediately spot the edge cases that will break it. Temporal logic is not abstract theory to you, it is the language you use to describe what correct behavior actually means. You have worked with tools like Jasper or VC-Formal enough to know their strengths, their quirks, and when to push back on a proof that looks complete but is not.

Mentoring comes naturally because you remember what it was like to debug your first failed assertion at 2am, and you would rather teach someone to set up a clean proof than fix their setup later. You can sit with a design team in Bangalore, walk through a formal verification plan, and leave them understanding not just what you are checking but why it matters.

What You'll Be Doing

• Build and maintain an end-to-end formal verification flow that integrates cleanly into the broader verification process, not a standalone tool that lives in a corner


• Create formal verification plans that identify the key behaviors worth proving, then develop the assertions, assumptions, and cover properties that actually close on those behaviors


• Guide design and verification engineers on effective use of formal tools, reviewing setups and proofs to catch issues before they become blockers


• Maintain and extend assertion libraries that work for both simulation and formal contexts, ensuring consistency across verification approaches


• Apply formal techniques like bounded model checking, induction, and abstraction to prove correctness of complex RTL designs


• Debug RTL when proofs fail, tracing back from a counterexample to the root cause in the design or the verification environment


• Train team members and mentor junior engineers on formal methods, assertion-based verification, and debugging strategies

The Impact You Will Have

• Catch design bugs that simulation would miss, preventing costly respins and schedule slips downstream


• Raise the quality bar for digital designs across Synopsys products by making formal verification a standard part of the process, not an afterthought


• Accelerate verification closure by proving corner cases formally instead of writing thousands of directed tests hoping to hit them


• Build verification infrastructure that other engineers can use effectively, multiplying your impact across the team


• Improve design quality at the source by working closely with RTL designers to identify and fix issues early


• Contribute to the silicon and IP solutions that power everything from AI accelerators to automotive systems


• Strengthen the formal verification capability of the Bangalore team through knowledge sharing and hands-on mentorship

What You'll Need

• 8+ years of industry experience in digital design or verification, with at least 5 years focused on formal verification techniques


• Deep understanding of digital logic, RTL design patterns, and the synthesis and timing flows that turn RTL into gates


• Hands-on experience with Verilog or SystemVerilog and the ability to read and debug complex RTL quickly


• Solid grasp of temporal logic and assertion-based verification, including SVA or PSL


• Experience with at least one formal verification tool such as Jasper or VC-Formal, including setup, proof strategies, and debug


• Track record of using formal methods to close verification on complex projects, not just toy examples


• Bachelor’s or master’s in computer science or electrical engineering; experience with Python, Perl, or Shell scripting is a plus

Who You Are

• You can look at a failed proof, trace the counterexample back through the design, and figure out whether the bug is in the RTL, the assumptions, or the assertion itself


• You explain formal verification concepts to someone who has only done simulation-based verification in a way that makes them want to try it, not run away from it


• You push back when a verification plan is too vague or when assumptions are hiding real design issues instead of simplifying the problem space


• You stay organized across multiple verification tasks, keeping track of which proofs are complete, which are bounded, and which need more work


• You collaborate effectively with geographically distributed teams, whether that means a design review over video or a detailed written explanation of a proof strategy


• You mentor junior engineers by showing them how to think about formal verification, not just how to run a tool

The Team You'll Be Part Of

You will be part of the Solutions Group at the Bangalore Design Center, working with a team focused on delivering high-quality digital designs and verification solutions. The team values learning and growth, and you will have opportunities to work with talented engineers across different geographies and disciplines.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.