Senior R&D Software Engineer - Formality Verification

Synopsys India Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Synopsys India Pvt Ltd is seeking a Senior Staff Engineer for the Formality R&D team in Bengaluru. You will architect and own the Formality verification engine, driving performance, memory, and scalability improvements for multi-core platforms.

The role requires deep C++ proficiency, strong data structures knowledge, and experience with Verilog/SystemVerilog. You will mentor teams, handle complex escalation issues, and contribute to architectural evolution of flagship EDA tools.

Qualifications

• BE/B.Tech in Computer Science, Electrical, or Electronics Engineering with strong relevant experience, or an MS/ PhD in a related discipline.
• 5+ years (BE/B.Tech),3+ years (MS), or 2+ years (PhD) of professional software development experience in large, production C++ codebases.

Responsibilities

• Architect, develop, and own core infrastructure of the Formality verification engine.
• Drive runtime, memory, and capacity improvements profiling production designs and re-engineering hotspots to deliver step-function gains.
• Design and harden parallel architectures to scale equivalence checking to modern multi-core machines.
• Take end-to-end technical ownership of complex customer escalations rooted in layers — reproducing, root-causing, fixing, and adding safeguards.

Skills

C++

Data structures and algorithms

Performance optimization

HDLs knowledge

Communication skills

Education

BE/B.Tech in CS/EE/ECE

MS/PhD in related discipline

Tools

Verilog

SystemVerilog

Python

Shell scripting

Job description

R&D Engineering, Staff Engineer - Formality Team
Job ID 17730
Country India
City Bengaluru
Date Posted 04-Jun-2026
Job Category Engineering
Job Subcategory R&D Engineering
Hire Type Employee
Remote Eligible No

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

What You'll Be Doing

• Architect, develop, and own core infrastructure of the Formalityverificationengine.
• Drive runtime, memory, and capacity improvements profiling production designs and re-engineering hotspots to deliver step-function gains.
• Design and hardenparallelarchitecturesto scale equivalence checkingtomodernmulti-core machines.
• Take end-to-end technical ownership of complex customer escalations rooted in layers — reproducing, root-causing, fixing, and adding the safeguards that prevent regression.
• Initiatedesign reviews, raise the bar on code quality and unit-test coverage.
• Collaborate across teams to enable the abstractions needed for future capabilities.

The Impact You Will Have

Define the structural and performance ceiling of Formality, directly enabling our customers to sign off larger and more complex designs with confidence. Strengthen the long-term architectural foundation of a flagship Synopsys product trusted across every major semiconductor company. Influence the technical direction of the team through design leadership, mentorship, and a strong example of engineering rigor. Help accelerate the tape-out cycles of the chips that power AI, mobile, automotive, and high-performance computing worldwide.

What You'll Need

• BE/B.Techin Computer Science, Electrical, or Electronics Engineering with strong relevant experience, or an MS / PhD in a related discipline.
• 5+ years (BE/B.Tech),3+ years (MS), or 2+ years (PhD) of professional software development experience in large, production C++ codebases, with demonstrated module ownership and technical leadership on non-trivial features.
• Expert command of modern C++, the STL, templates, and idiomatic memory and lifetime management for performance-sensitive systems.
• Strong fundamentals in data structures and algorithms — graphs, hash tables, trees, traversal andBDD— with a track record of applying them to real engineering problems.
• Demonstrated ability to profile, diagnose, and optimize for runtime, memory, and scalability on multi-million-instance workloads.
• Working knowledge of HDLs (Verilog /SystemVerilog/ VHDL) and digital design fundamentals; familiarity with synthesis, equivalence checking, or related EDA flows is strongly preferred.
• Comfort with TCL, Python, and shell scripting for tool infrastructure, regressions, and developer tooling.
• Exposure to AI-assisted developer tools such as Cursor or GitHub Copilot, and a curiosity for adopting modern productivity practices.
• Excellent written and verbal communication, with the ability to lead technical discussions across teams.

Who You Are

A systems thinker who understands how a small change deep in thesystemripples through the entire product. A disciplined engineer who values measurement over intuition and tests over hope. A mentor and collaborator who lifts the technical quality of everyone around you. A pragmatic problem-solver who balances long-term architecture with short-term delivery. A continuous learner who keeps pace with advances in C++ and EDA methodology.

The Team You'll Be A Part Of

You will join the Formality R&D team — the group responsible for the structural backbone of one of the industry's most established formal equivalence checking tools. We own the data, the infrastructure, and the performance characteristics that every other Formality capability is built upon. The team values deep technical ownership, careful engineering, and a culture where strong opinions are tested against data. You will work alongside experienced engineers solving problems at the limits of design size, with broad exposure to formal verification, synthesis, and large-scale software systems.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

#TPG At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Experience Level Senior Level