R&D Engineer IC Design

Broadcom; Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

Broadcom in Bengaluru seeks a seasoned DFT engineer to drive several phases of SoC DFT activities, including ATPG, MBIST and JTAG. You will contribute to DFT insertion, vector generation and post-silicon debugging, while collaborating with cross-functional teams and external customers.

The candidate should have 8+ years of relevant experience or a Master's with 6+ years, and strong problem-solving and communication skills. Preference for exposure to Siemens/Mentor DFT tools is a plus.

Qualifications

• In-depth knowledge of DFT concepts is required.
• Experience with ATPG, MBIST and JTAG is essential.
• Experience with DFT insertion and verification, pattern generation, and coverage improvement is expected.
• Proficient in vector simulation and post-silicon debugging.
• Strong problem solving and debugging skills; scripting (Perl, Shell) is a plus.

Responsibilities

• Work on DFT architecture, test insertion, verification and post-silicon debug for Broadcom APD designs.
• Collaborate with Physical Design & STA teams for DFT timing closure.
• Interact with external customers as needed and supervise team members when required.

Skills

DFT concepts

ATPG

MBIST

JTAG

vector simulation

scripting

TestKompress

Fastscan

Education

Bachelor's degree

Master's degree

Tools

TestKompress

Fastscan

Job description

Job Description:

The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.

Job Description:

The candidate should have in-depth knowledge of DFT concepts and should be well experienced in various aspects of DFT -ATPG, MBIST & JTAG. The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug. Strong problem solving & debugging skills are a must. Expertise in scripting languages such as perl, shell, etc. is an added advantage. Experience with either Seimens-Mentor Graphics DFT tools (TestKompress, Fastscan) is highly desirable.

The candidate should have worked with team across multiple geographies. The candidate should be able to handle his/her work independently and also supervise the work of other team members as required. The candidate should possess excellent communication skills.

Educational qualification & Experience Level : Bachelor’s degree with 8+ years of relevant experience or Master’s degree with 6+ years of relevant experience

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