DFT Staff Engineer

Broadcom; Pune District; On-site; INR 1,200,000 - 2,100,000; Full time

Job summary

Broadcom is seeking a seasoned SoC DFT engineer to handle architecture, test insertion, and verification across APD designs. You will generate patterns, improve coverage, and work with the Physical Design and STA teams to ensure DFT timing closure.

The role may involve direct interaction with external customers. The ideal candidate has deep DFT knowledge (ATPG, MBIST, IJTAG) and experience in vector simulation, DFT insertion, and post-silicon debugging, with strong scripting abilities (Perl,

Qualifications

• Bachelor's degree with 8+ years or Master's with 6+ years of relevant experience.
• In-depth knowledge of DFT concepts including ATPG, MBIST and IJTAG.
• Strong debugging, scripting (Perl, Shell), and communication skills.

Responsibilities

• Work on various phases of SoC DFT activities for Broadcom APD designs (DFT architecture, test insertion, verification).
• Collaborate with Physical Design & STA teams for DFT mode timing closure.
• Interact with external customers as needed; drive pattern generation and coverage improvements.

Skills

DFT concepts

ATPG

MBIST

IJTAG

Pattern generation

Vector simulation

Scripting: Perl/Shell

Education

Bachelor's degree in relevant field

Master's degree in relevant field

Tools

Mentor Tessent Shell

Job description

Job Description:
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)'s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.

Job Description:
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)'s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.
The candidate should have in-depth knowledge of DFT concepts and should be experienced in various aspects of DFT -ATPG, MBIST & IJTAG. The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug. Strong problem solving & debugging skills are a must. Expertise in scripting languages such as perl, shell, etc. is an added advantage.
Experience with either Mentor Graphics DFT tools (Tessent Shell) is highly desirable.
The candidate should have worked with team across multiple geographies. The candidate should be able to handle his/her work independently. The candidate should possess excellent communication skills.
Educational qualification & Experience Level : Bachelor's degree with 8+ years of relevant experience or Master's degree with 6+ years of relevant experience