DFT Senior Engineer

Broadcom; Pune District; On-site; INR 2,400,000 - 3,600,000; Full time

Job summary

Broadcom APD (ASIC Product Division) seeks a DFT engineer to work across multiple DFT activities including architecture, test insertion, and verification for diverse SoC designs. The role involves pattern generation, coverage improvement, and post-silicon debugging to meet test metrics.

Ideal candidates should have deep DFT knowledge, experience with ATPG/MBIST/IJTAG, and scripting skills (Perl/Shell). Interaction with global teams and customers is possible.

Qualifications

• Bachelor's degree or higher with relevant experience in DFT.
• Experience in DFT insertion, verification and pattern generation.
• Strong problem solving and debugging skills; good communication.

Responsibilities

• Work on DFT Architecture, test insertion and verification for Broadcom APD ASICs.
• Develop pattern generation and improve coverage for DFT.
• Perform post-silicon debug and yield improvement activities.
• Collaborate with Physical Design & STA teams for DFT timing closure.
• Interact with external customers as needed.

Skills

DFT concepts

ATPG

MBIST

IJTAG

vector simulation

post-silicon debug

scripting (perl, shell)

communication skills

Education

Bachelor's degree

Master's degree

Tools

Mentor Graphics Tessent Shell

Job description

Job Description

The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)'s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.

The candidate should have in-depth knowledge of DFT concepts and should be experienced in various aspects of DFT -ATPG, MBIST & IJTAG. The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug. Strong problem solving & debugging skills are a must. Expertise in scripting languages such as perl, shell, etc. is an added advantage.

Experience with either Mentor Graphics DFT tools (Tessent Shell) is highly desirable.

The candidate should have worked with team across multiple geographies. The candidate should be able to handle his/her work independently. The candidate should possess excellent communication skills.

Educational qualification & Experience Level : Bachelor's degree with 5+ years of relevant experience or Master's degree with 3+ years of relevant experience