DFT Senior Engineer

Broadcom; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Broadcom is seeking a seasoned DFT Engineer to work on SoC DFT activities for APD ASIC designs. You will contribute to DFT architecture, test insertion, verification, pattern generation, and coverage improvements to meet product test metrics.

You will collaborate with the Physical Design & STA teams for DFT timing closure and may interact with external customers. Candidates should have 5+ years in DFT and strong debugging and scripting skills, with experience in Tessent Shell being a plus.

Qualifications

• Deep knowledge of DFT concepts and practice in ASIC designs.
• Experience in DFT-ATPG, MBIST and IJTAG.
• Hands-on experience with DFT insertion and verification.
• Pattern generation, coverage improvement and vector simulation.
• Strong debugging, problem solving and communication skills.
• Experience with scripting languages (Perl, shell) is a plus.
• Experience with Mentor Graphics Tessent Shell is highly desirable.
• Ability to work across geographies and independently.

Responsibilities

• Work on DFT architecture and test insertion for Broadcom APD ASICs.
• Verify DFT implementations and improve pattern coverage.
• Collaborate with Physical Design & STA for DFT timing closure.
• Interface with external customers as needed.

Skills

DFT concepts

ATPG

MBIST

IJTAG

Pattern generation

Vector simulation

Post-silicon debug

Scripting (Perl/Shell)

Communication skills

Problem solving

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical Engineering or related field

Tools

Tessent Shell

Perl

Shell scripting

Job description

Job Description

The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)'s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.

The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)'s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.

The candidate should have in-depth knowledge of DFT concepts and should be experienced in various aspects of DFT -ATPG, MBIST & IJTAG. The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug. Strong problem solving & debugging skills are a must. Expertise in scripting languages such as perl, shell, etc. is an added advantage.

Experience with either Mentor Graphics DFT tools (Tessent Shell) is highly desirable.

The candidate should have worked with team across multiple geographies. The candidate should be able to handle his/her work independently. The candidate should possess excellent communication skills.

Educational qualification & Experience Level : Bachelor's degree with 5+ years of relevant experience or Master's degree with 3+ years of relevant experience

R027636