R&D Engineer IC Design

Broadcom, Inc.; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Broadcom is seeking an experienced R&D Engineer specializing in IC DFT to work on architecture, insertion and verification for ASIC designs. You will coordinate with Physical Design & STA teams to achieve timing closure in DFT mode and may interact directly with external customers.

Strong debugging skills and scripting in Perl/Shell are valued in this role. The candidate should have 8+ years of relevant experience with a Bachelor’s degree or 6+ years with a Master’s degree, and familiarity with

Qualifications

• Bachelor’s degree with 8+ years of relevant experience or Master’s degree with 6+ years of relevant experience.
• Expertise in DFT concepts including ATPG, MBIST and JTAG.
• Experience with DFT insertion & verification, pattern generation and coverage improvement.
• Vector simulation and post-silicon debug experience is required.
• Strong problem solving and debugging skills; scripting in Perl/Shell is a plus.
• Experience with Mentor Graphics DFT tools (TestKompress, Fastscan) is highly desirable.
• Ability to collaborate across geographies and work independently or lead others.

Responsibilities

• Work on various phases of SoC DFT activities for ASIC product designs.
• Engage in DFT architecture, test insertion, verification and coverage improvement.
• Coordinate with Physical Design & STA teams for DFT timing closure.
• Interact with external customers as needed; mentor teammates as required.

Skills

DFT concepts

ATPG

MBIST

JTAG

Pattern generation

Vector simulation

Scripting (Perl/Shell)

Education

Bachelor’s degree with 8+ years of relevant experience

Master’s degree with 6+ years of relevant experience

Tools

Mentor Graphics DFT tools

Job description

R&D Engineer IC Design### R&D Engineer IC DesignApply: IND-Bangalore Electronic City - S1: Full time: Posted Yesterday: R027599**Please Note:****1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)****2. If you already have a Candidate Account, please Sign-In before you apply.**## **Job Description:**The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers. The candidate should have in-depth knowledge of DFT concepts and should be well experienced in various aspects of DFT -ATPG, MBIST & JTAG. The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug. Strong problem solving & debugging skills are a must. Expertise in scripting languages such as perl, shell, etc. is an added advantage. Experience with Mentor Graphics DFT tools (TestKompress, Fastscan) is highly desirable. The candidate should have worked with team across multiple geographies. The candidate should be able to handle his/her work independently and also supervise the work of other team members as required. The candidate should possess excellent communication skills. Educational qualification & Experience Level : Bachelor’s degree with 8+ years of relevant experience or Master’s degree with 6+ years of relevant experience**Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.****If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.**