Principal Physical Design Engineer

Mulya Technologies; Bengaluru; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

Mulya Technologies in Bengaluru seeks an experienced Physical Design Engineer (10–14 years) with strong RTL-to-GDS implementation expertise and Cadence Innovus proficiency. The role requires hands-on SystemVerilog and scripting (Python/Perl), and a track record of delivering high-volume shipped products.

You will work on advanced-node Block/SoC designs, optimize PPA, and collaborate with RTL/Flows teams to converge designs to meet power, frequency, and area targets.

Qualifications

• 10–14 years of hands-on experience in physical design.
• Bachelor's or Master's degree in Electronics, Electrical or Computer Engineering.

Responsibilities

• Drive physical design implementation from RTL to GDS for Block/SoC designs on advanced nodes.
• Collaborate with RTL and flows teams to converge designs to meet power, frequency and area targets.
• Demonstrate expertise in SystemVerilog and scripting (Python/Perl).
• Work at subsystem level with hierarchical blocks and proven shipped-high-volume products.

Skills

RTL-to-GDS

SystemVerilog

Python scripting

Perl scripting

PPA optimization

Education

Bachelor's in Electronics/Electrical/Computer Engineering

Master's in Electronics/Electrical/Computer Engineering

Tools

Cadence Innovus

Job description

We are looking for an experienced Physical Design Engineer (10-14 Years) with strong expertise in RTL-to-GDS implementation, Cadence Innovus, advanced-node Block/SoC designs, and PPA optimization. Candidates should have hands-on System Verilog + Python/Perl scripting experience and a proven track record of delivering high-volume shipped products.

What You\'ll Drive & Bring to the Role

• Experience in Physical Design implementation (from RTL to GDS) at Block or SoC designs on advanced process nodes
• Expertise and experience with industry-standard CAD tools from Cadence-Innovus.
• Experience in collaborating with RTL design and Flows teams to drive feasibility studies and converge Block/SoC designs to meet target power, frequency, and area targets.
• Expert knowledge of System Verilog, as well as Perl, Python or other scripting languages.
• Worked at Subsystem level and good experience at Hierarchy block/s.
• Proven track record of execution on products which have shipped in high-volume.

Required Qualifications

Bachelor\'s or Master\'s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related discipline with 10-14 yrs of work experience.