Principal Engineer – Physical Design

Upscale; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Upscale, Inc. is seeking a Principal Engineer - Physical Design in Bengaluru to lead the implementation of complex ASIC/SoC blocks from RTL to GDSII. You will drive design execution, define physical strategies, and mentor engineers to achieve best-in-class PPA across advanced nodes.

You will own floorplanning, CTS, routing, timing closure, and signoff at block and top levels, collaborating with RTL, DFT, STA, and power teams. Strong scripting skills and leadership are essential.

Qualifications

• 10-15+ years of deep-submicron physical design for complex SoCs/ASICs.
• Expertise in Cadence Innovus PNR flow.
• Strong STA (PrimeTime), IR/EM (Voltus), and DRC/LVS (Calibre) know-how.
• Solid RC extraction, clock mesh/tree design, power intent, and hierarchical design methods.
• Experience with 5 nm / 3 nm / N3E/N3P nodes and foundry signoff flows.
• Excellent analytical, debugging, and problem-solving skills.
• Proficient scripting with Tcl, Python, or Perl for automation.
• Strong communication and leadership to coordinate global teams.

Responsibilities

• Own end-to-end physical design implementation for large hierarchical blocks from floorplanning to GDSII signoff.
• Develop and optimize flows for placement, CTS, routing, and timing closure.
• Analyze and optimize IR drop, EM, congestion, and power to meet targets.
• Collaborate with RTL, DFT, STA, and power teams to resolve cross-domain issues.
• Define and maintain best practices, scripts, and automation flows (Tcl, Python, or Make).
• Lead timing, physical verification (DRC/LVS), and ECO closure at block/top level.
• Provide leadership for floorplan architecture, partitioning, and clock distribution strategies.
• Drive MCMM analysis and signoff consistency across corners and modes.
• Partner with CAD/Foundry teams for technology eval and library bring-up.
• Mentor junior engineers and promote a strong PD culture.

Skills

Deep-submicron PD

Cadence Innovus

PrimeTime

Voltus

Calibre

5/3 nm nodes

RC extraction

Clock design

Tcl/Python scripting

Leadership & mentoring

Cross-functional collaboration

Education

Master's Degree in Electrical / Electronics / VLSI Engineering

Tools

Cadence Innovus PNR

PrimeTime

Voltus

Calibre

Job description

Why join Upscale, Inc.

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

Why join Upscale, Inc.

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard.

Role Summary:

As a Principal Engineer - Physical Design, you will be responsible for leading the implementation of complex, high-performance ASIC/SoC blocks from RTL to GDSII. You will drive design execution, define physical implementation strategies, and mentor engineers to achieve best-in-class Power, Performance, and Area (PPA) across advanced technology nodes.

Key Responsibilities:

• Own end-to-end physical design implementation for large hierarchical blocks, from floorplanning to GDSII signoff
• Develop and optimize flows for placement, clock tree synthesis (CTS), routing, and timing closure
• Analyze and optimize IR drop, EM, congestion, and power to meet stringent chip targets
• Collaborate with RTL, DFT, STA, and power teams to resolve cross-domain issues and ensure robust closure
• Define and maintain best practices, scripts, and automation flows (Tcl, Python, or Make-based)
• Lead timing, physical verification (DRC/LVS), and ECO closure at the block and top level
• Provide technical leadership for floorplan architecture, partitioning, and clock distribution strategies
• Drive design convergence on multi-corner multi-mode (MCMM) analysis and ensure signoff consistency
• Partner with CAD and Foundry teams for technology evaluation, library bring-up, and methodology improvement
• Mentor and guide junior engineers, fostering a strong technical culture within the PD organization

Required Skills & Experience:

• 10-15+ years of experience in deep-submicron physical design for complex SoCs or ASICs
• Proven expertise in Cadence Innovus PNR tool
• Strong understanding of STA (PrimeTime), IR/EM (Voltus), and DRC/LVS (Calibre) flows
• Solid grasp of RC extraction, clock mesh/tree design, power intent , and hierarchical design methodologies
• Experience in advanced process nodes (5 nm / 3 nm / N3E/N3P) with exposure to foundry signoff flows.
• Excellent analytical, problem-solving, and debugging skills with attention to detail
• Proficiency in Tcl, Perl, or Python scripting for automation and flow development
• Strong communication and leadership skills to coordinate across global cross-functional teams

Preferred Skills:

• Experience with full-chip integration, floorplan architecture, and package interaction
• Familiarity with machine learning or AI-based flow optimization is a plus
• Masters Degree in Electrical / Electronics / VLSI Engineering preferred

Key Traits for Success:

• Strategic thinker with deep technical insight
• Collaborative mindset and mentoring spirit
• Passion for continuous learning and process excellence
• Ability to balance innovation with execution discipline

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

Equal Opportunity

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

Accessibility & Accommodations

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at [e-mail]—we’re happy to help. Note: This inbox is only for accommodation requests.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.