Senior Manager – Physical Design

Upscale, Inc.; Bengaluru; On-site; INR 4,200,000 - 6,200,000; Full time

Benefits offered by this job

Equal Opportunity Employer

Accommodation support

Job summary

Upscale, Inc. seeks a Senior Back End Manager - Physical Design to lead high-performance ASIC/SoC implementation teams from RTL to GDSII. You will drive execution strategy, build scalable methodologies, and ensure design convergence across advanced nodes.

With 15–20 years of PD experience, you will manage multiple blocks, collaborate with cross-functional teams, and deliver silicon on aggressive PPA targets. A strong leadership and automation mindset is essential.

Qualifications

• 15-20 years of ASIC/SoC Physical Design experience with large back-end teams.
• Successful tape-out experience on advanced technology nodes.
• Expertise in floorplanning, power planning, placement, CTS, routing, ECO, signoff.
• Strong Cadence Innovus based implementation flows.
• STA (PrimeTime), IR/EM analysis (Voltus/RedHawk), Calibre/ICV extraction.
• Hands-on with 5 nm / 3 nm / N3E/N3P and foundry signoff requirements.
• Hierarchical design, multi-voltage, UPF, clock distribution, MCMM closure.
• Scripting in Tcl, Perl, Python; strong automation mindset.
• Leadership, communication, and cross-functional collaboration.

Responsibilities

• Lead and manage a team of Physical Design engineers for ASIC/SoC signoff.
• Own back-end execution: floorplanning, placement, CTS, routing, timing closure.
• Drive project planning, resource allocation, risk identification and mitigation.
• Provide architecture guidance on partitioning, clocking, and power strategy.
• Collaborate with Architecture, RTL, DFT, STA, CAD, Foundry, and PM teams.
• Drive convergence on PPA, timing, power, IR/EM, DRC/LVS, and manufacturability.
• Establish execution flows, quality checks, and automation best practices.
• Mentor engineers and build a culture of ownership and excellence.

Skills

Cadence Innovus

PrimeTime STA

IR/EM analysis

Calibre/ICV

5nm/3nm nodes

UPF

Clock distribution

Scripting (Tcl/Perl/Python)

Leadership

Education

Master’s Degree in Electrical Engineering / Electronics / VLSI

Tools

Voltus

RedHawk

Calibre

Job description

Why join Upscale, Inc.

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking-where performance, scale, and execution are critical.Our team is talent-dense andhigh-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI-Upscale is where you can produce meaningful work at the frontier—and operate at a high standard.

Role Summary:
As a Senior Back End Manager - Physical Design, you will be responsible for leading high-performance ASIC/SoC physical implementation teams delivering complex designs from RTL to GDSII. You will drive execution strategy, build scalable methodologies, manage technical execution across multiple blocks/subsystems, and ensure successful design convergence across advanced technology nodes.

The role requires a strong technical leader with hands-on expertise in physical design, proven ability to manage engineering teams, and experience delivering large-scale silicon programs with aggressive Power, Performance, Area, and Schedule targets.

Key Responsibilities:

Lead and manage a team of Physical Design engineers responsible for implementation and signoff of complex ASIC/SoC designs.

Own overall back-end execution strategy including floorplanning, placement, CTS, routing, timing closure, physical verification, and tape-out readiness.

Drive project planning, resource allocation, execution tracking, risk identification, and mitigation across multiple design milestones.

Provide technical leadership for architecture decisions including hierarchy definition, partitioning strategy, clock architecture, power planning, and implementation methodology.

Collaborate closely with Architecture, RTL, DFT, STA, CAD, Packaging, Foundry, and Program Management teams to achieve successful silicon delivery.

Drive convergence across PPA, timing, power, IR/EM, signal integrity, DRC/LVS, reliability, and manufacturability requirements.

Establish robust execution methodologies, quality checks, automation flows, and best practices across the Back End organization.

Review design quality at key milestones and ensure strong execution discipline through structured reviews and predictable delivery.

Lead debug and resolution of complex design challenges across timing, congestion, power, physical verification, and ECO implementation.

Partner with CAD and EDA vendors to improve flows, evaluate new technologies, and enhance design productivity.

Mentor engineers, technical leads, and future leaders while building a culture of ownership, innovation, accountability, and engineering excellence.

Required Skills & Experience:

15-20 years of experience in ASIC/SoC Physical Design with strong experience managing large Back End implementation teams.

Proven track record of delivering complex SoC designs successfully through tape-out on advanced technology nodes.

Deep expertise in physical implementation flows including floorplan, power planning, placement, CTS, routing, ECO, and signoff closure.

Strong experience with Cadence Innovus based implementation flows.

Expert-level understanding of STA (PrimeTime), IR/EM analysis (Voltus/RedHawk), physical verification (Calibre/ICV), and extraction methodologies.

Hands-on experience with advanced process nodes (5 nm / 3 nm / N3E/N3P) and foundry signoff requirements.

Strong understanding of hierarchical design methodologies, multi-voltage designs, UPF, clock distribution strategies, and MCMM closure.

Experience defining metrics, dashboards, quality checks, and execution processes for predictable project delivery.

Strong scripting and automation mindset using Tcl, Perl, Python, or equivalent languages.

Excellent leadership, communication, decision-making, and cross-functional collaboration skills.

Preferred Skills:

Experience leading full-chip implementation and large subsystem ownership.

Exposure to AI/HPC/networking class SoCs with aggressive performance and power requirements.

Experience building teams, defining organizational processes, and scaling execution methodologies.

Knowledge of ML-driven EDA optimization and next-generation design methodologies is a plus.

Master’s Degree in Electrical Engineering / Electronics / VLSI Engineering preferred.

Key Traits for Success:

Strong technical depth combined with execution leadership.

Ownership mindset with the ability to drive complex programs to closure.

Ability to identify risks early and create structured recovery plans.

Passion for building high-performing teams and mentoring engineers.

Data-driven decision making with focus on quality, predictability, and continuous improvement.

Ability to balance innovation, schedule pressure, and silicon delivery excellence.

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

Equal Opportunity

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

Accessibility & Accommodations

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us [e-mail]—we’re happy to help. Note: This inbox is only for accommodation requests.