Principal Engineer

Cadence Design Systems (India) Pvt. Ltd.; Hyderabad; Sur place; INR 4 000 000 - 7 000 000; Plein temps

Résumé du poste

Cadence Design Systems (India) Pvt. Ltd. seeks an experienced Analog/Mixed-Signal Design Engineer for high-speed SerDes clocking and bias circuits. You will design, optimize, and validate clocking generation/distribution, bias/reference circuits, and perform extensive simulations to ensure tight phase-noise and jitter specs.

You will collaborate with TX/RX, layout, and modeling teams, mentor juniors, and contribute to architecture decisions and design reviews for next-gen SerDes products.

Qualifications

• 8+ years hands-on analog/mixed-signal IC design experience.
• Strong background in high-speed SerDes clocking architectures.
• Proficiency with Cadence tools for schematic, layout, and simulation.

Responsabilités

• Design and optimize high-speed clocking and bias circuits for SerDes PHYs.
• Develop PLL/DLL/FD, clock generation, distribution, and buffers.
• Analyze phase noise, jitter, duty cycle, and power, with simulations.
• Perform PVT, Monte Carlo, mismatch, and reliability analyses.
• Collaborate with cross-functional teams and drive design reviews.

Connaissances

Analog/Mixed-Signal IC Design

Clocking Architectures

PLL/CDR/DLL

VCO/LC VCO

Bias/Reference Circuits

Jitter/Phase Noise

Monte Carlo/PVT/MC Analysis

Post-layout Simulations

High-Speed SerDes

Cadence Virtuoso/ADE

Spectre/Analog Solvers

Outils

Cadence Virtuoso/ADE

Spectre

Description du poste

We are looking for an experienced Analog/Mixed-Signal Design Engineer with strong expertise in clocking and bias circuits for high-speed SerDes. The candidate will be responsible for designing, optimizing, and validating clock generation, clock distribution, bias/reference, and related analog circuits for advanced-node high-speed SerDes products.

Key Responsibilities

• Design and develop high-speed clocking and bias circuits for SerDes PHYs.
• Design and optimize PLL/DLL, CDR, clock generation, clock distribution, dividers, buffers, and related circuits.
• Develop robust bias generation, current/voltage references, bias distribution, and startup circuits.
• Analyze and optimize phase noise, jitter, duty cycle, skew, clock accuracy, and power consumption.
• Perform detailed PVT, Monte Carlo, mismatch, corner, and reliability analysis.
• Drive circuit design to meet performance, power, area, and jitter specifications.
• Work closely with TX/RX, analog, digital, layout, modeling, and system teams to achieve end-to-end SerDes performance.
• Perform pre-layout and post-layout simulations, including parasitic extraction and signoff.
• Debug circuit issues related to noise coupling, supply sensitivity, substrate coupling, IR drop, and process variation.
• Support silicon bring-up, characterization, and post-silicon debug.
• Contribute to circuit architecture, design reviews, methodology improvements, and technical documentation.
• Mentor junior engineers and provide technical leadership for clocking and bias blocks.

Required Qualifications

• 8+ years of hands-on experience in Analog/Mixed-Signal IC Design.
• Strong experience with high-speed SerDes clocking architectures.
• Expertise in one or more of:
  • PLL / CDR / DLL
  • LC/VCO or Ring VCO
  • Charge Pump and Loop Filter
  • Frequency Divider / Clock Divider
  • High-speed clock buffers and clock distribution
  • Bias generation and reference circuits
  • Bandgap/current reference circuits
  • Low-jitter clock generation
• Strong understanding of jitter, phase noise, loop dynamics, clock skew, supply noise, and substrate noise.
• Experience with advanced CMOS technology nodes and low-voltage analog design.
• Strong understanding of PVT variation, mismatch, Monte Carlo, and statistical analysis.
• Hands-on experience with Cadence Virtuoso/ADE, Spectre or equivalent simulation tools.
• Experience with post-layout simulation and extracted parasitic analysis.
• Good understanding of high-speed protocols such as PCIe, USB, Ethernet/SerDes, SATA, or similar interfaces.