High-Speed SerDes Design Engineer

Powai Labs; Mumbai; On-site; INR 1,500,000 - 2,300,000; Full time

Job summary

Powai Labs in Mumbai seeks a seasoned SerDes architecture engineer with deep expertise in high-speed analog/mixed-signal design and DSP-based equalization. You will work on 28G–224G SerDes generations and contribute to silicon bring-up, eye-diagram analysis, and jitter optimization, collaborating with cross-functional teams to deliver robust SerDes solutions.

This role requires hands-on verification and protocol-level understanding to ensure reliable performance across generations.

Qualifications

• Experience in high-speed analog front-end design including CTLE, DFE, samplers, comparators, CDR loops.
• Proficiency with clocking systems such as PLLs, phase interpolators, duty-cycle correction, jitter optimization.
• Hands-on silicon bring-up and characterization including eye diagrams, BER testing, jitter breakdown.

Skills

High-speed analog front-end design

Clocking systems

Silicon bring-up & characterization

Job description

A strong SerDes architecture engineer will demonstrate deep expertise in high‑speed analog/mixed‑signal design, DSP‑based equalization, protocol‑level understanding, and silicon‑proven experience across 28G–224G SerDes generations.

Required Skills and Knowledge

High‑speed analog front‑end design: CTLE, DFE, samplers, comparators, CDR loops.

Clocking systems: PLLs, phase interpolators, duty‑cycle correction, jitter optimization.

Silicon bring‑up & characterization: eye diagrams, BER testing, jitter breakdown.