Principal SerDes Analog Design

Omni Design Technologies, Inc.; Hyderabad; Hybrid; INR 4,000,000 - 7,000,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

Omni Design Technologies, Inc. in Hyderabad is seeking a senior engineer for SerDes analog design focused on 100Gbps+ wireline technologies.

You will develop cutting-edge circuits and architectures for ultra-high-speed systems, guiding from initial spec through layout supervision and silicon evaluation to market introduction. The role requires 10+ years in analog or mixed-signal IC development, bench testing, and strong Cadence/simulation experience, with collaboration across multinational teams

Qualifications

• 10+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes.
• Experience with SERDES blocks: ADC/DAC, CTLE, CDR, PLL.
• Proven track record of taking designs to production.
• Ability to work with customers to define products addressing needs.
• Experience evaluating silicon on bench with standard lab equipment.
• Strong understanding of transistor-level circuit design, including noise and mismatch analysis.
• Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks.
• Familiar with layout parasitic extraction tools and layout-dependent impairments in advanced CMOS processes.
• Experience with Cadence schematic capture, Virtuoso, Spectre and/or HSPICE simulations.
• MATLAB understanding preferred but not mandatory.
• Familiar with electromigration and ESD design in submicron CMOS.
• Ability to work independently and meet schedules.
• Strong written and verbal communication across geographic teams.

Responsibilities

• Develop circuits and architectures for ultra-high-speed SerDes (100Gbps+) wireline tech.
• Lead design and layout supervision from spec to silicon evaluation and product introduction.

Skills

Analog/mixed-signal design

SerDes design

High-speed circuit design

Transistor-level design

CMOS processes

Lab bench testing

Digital control blocks

Cadence Virtuoso

Spectre/HSPICE

MDL MATLAB (preferred)

Tools

Cadence schematic capture

Virtuoso

Spectre

HSPICE

EM/EDA tools

Job description

We are a leading provider of high-performance, ultra-low power IP cores optimized for advanced semiconductor nodes, enabling the development of cutting-edge systems-on-chip (SoCs) for applications such as 5G, AI, LiDAR, radar, networking, and IoT. Known for its innovative small geometry solutions, our expertise encompasses data converter IP cores ranging from 6-bit to 14-bit resolutions and sampling rates up to over 20 Gsps. F

Engineering – Analog/Mixed-Signal Circuit Design /

Full-time /

Hybrid

SerDes analog designer focusing 100Gbps+ wireline technologies (TX and RX path). The successful candidate in this role will develop cutting-edge circuits and architectures for ultra-high speed wireline communication systems, and will drive the development of high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market.

Qualifications

• 10+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes
• Familiarity with high-speed analog design and building block circuits for SERDES technology such as ADC/DAC, CTLE, CDR, PLL etc.
• Must have a track record of successfully taking designs to production
• Ability to work with customers to define products that address needs
• Must have experience with evaluating silicon on bench and familiarity with standard lab equipment
• Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis
• Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks
• Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools
• MATLAB understanding would be preferred but not mandatory
• Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process
• Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes
• Must be able to work independently, create and adhere to schedules
• Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations