Senior / Lead Physical Design Engineer

Axiado; Hyderabad; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

Axiado is seeking a highly experienced Senior/Lead Physical Design Engineer to drive backend implementation, signoff quality, methodology development, and project execution across ASIC programs in Hyderabad. The role blends technical leadership with hands-on execution from RTL handoff to tapeout.

The ideal candidate will define strategies, review vendor work, and mitigate risks while driving scalable, shift-left solutions and close collaboration with Architecture, RTL, DFT, and CAD teams.

Qualifications

• BS/MS in Electrical Engineering or related field.
• 8–12 years of ASIC Physical Design experience.
• Multiple successful tapeouts in advanced technology nodes.
• Strong experience owning implementation from RTL handoff through GDS signoff.
• Experience leading projects, reviewing deliverables, and coordinating work across multiple stakeholders.

Responsibilities

• Lead Physical Design activities from project planning through tapeout.
• Define implementation strategies, milestones, and execution plans.
• Work closely with contractors, consultants, and external implementation partners to ensure high-quality deliverables.
• Review implementation progress, identify risks, and drive corrective actions.
• Provide technical leadership across Physical Design, STA, DFT, RTL, and CAD teams.
• Drive design reviews and implementation readiness reviews.

Skills

Floorplanning

Hierarchical Planning

Power Planning

Placement & Optimization

Routing & Signal Integrity

STA & Timing Closure

ECO Methodologies

MCMM Flows

Power Optimization

Physical Verification Expertise

Debug complex signoff issues

Education

BS/MS in Electrical Engineering or related field

Tools

Calibre

IC Validator (ICV)

DRC

LVS

ERC

Density Closure

Physical Signoff

Job description

Axiado is building the future ofAI powereddigital infrastructure. We are afast-growing,well fundedsilicon, systems, and solutionscompany pioneering a newcategoryofsemiconductor called theTrusted Control/Compute Unit (TCU) that combinesadvanced hardware security,AI drivenresilience and efficiency, andreal-timeplatform management. Our technology protects the world’s most critical infrastructure—from data centers tonext generationcloud and AI platforms—by securing systems at thefoundation levels of hardware, independent of host CPUs and operating systems.

Founded in 2019and now over 150 employeesare strong, Axiado has evolved into a recognized leader in the convergence of AI, security, and silicon innovation. We partner with and are actively engaged in commercial programs with multiple Tier 1 industry leaders,validatingboth our technology and our long-term market trajectory.Axiado has also won numerousindustry awards for our ground-breaking products and technological innovations, includingbeing namedone ofFast Company’s 2025 Top 10 Most Innovative Companiesin Security,winning the2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliance’s 2025 “Start-Up to Watch” award.

At Axiado, developing breakthrough technology takes more than great engineering—it takes a team of exceptional people who collaborate boldly, challenge assumptions, and take pride in building what comes next. We value curiosity, execution, respect, and a shared desire to make a meaningful impact on the security and reliability of the digital world.

Job Description

We are looking for a highly experienced and hands-on Senior / Lead Physical Design Engineer to drive backend implementation, signoff quality,methodologydevelopment, and project execution across our ASIC programs.

This role combines technical leadership with hands-on execution. The successful candidate willbe responsible fordefining implementation strategies,establishingPhysical Design and Physical Verification methodologies, reviewing and guiding work performed by contractors and external vendors, and ensuring successful execution from RTL handoff throughtapeout.

The ideal candidate is a strong shift-left thinker who can proactivelyidentifyimplementation risks, influence architectural decisions, and drive scalable solutions whileremainingdeeply involved in technical problem solving.

Key Responsibilities

Technical Leadership & Project Execution

• Lead Physical Design activities from project planning throughtapeout.
• Define implementation strategies, milestones, and execution plans.
• Work closely with contractors, consultants, and external implementation partners to ensure high-quality deliverables.
• Review implementation progress,identifyrisks, and drive corrective actions.
• Provide technical leadership across Physical Design, STA, DFT, RTL, and CAD teams.
• Drive design reviews and implementation readiness reviews.

Physical Design Ownership

• Own block and full-chip implementation activities including:
  • Floorplanning
  • Power Planning
  • Placement
  • CTS
  • Routing
  • Timing Closure
  • ECO Implementation
  • Signoff Closure
• Drive performance, power, area, congestion, and timing optimization.

Physical Verification & Signoff

• Define and drive signoffmethodologyand closure strategy.
• Lead DRC, LVS, ERC, Antenna, Density, and Manufacturing rule closure.
• Review and sign off vendor deliverables related to physical verification.
• Debug complex signoff issues and drive root-cause resolution.

Methodology & Flow Development

• Develop and improve Physical Design methodologies, implementation recipes, and signoff flows.
• Drive automation initiatives to improve productivity and design quality.
• Establish best practices, checklists, and execution guidelines across projects.
• Promote shift-left methodologies to improve backend predictability and reduce project risk.

Cross-Functional Collaboration

• Partner with Architecture, RTL, DFT, Verification, Packaging, CAD, and Product teams.
• Influence design decisions through implementation-aware feedback.
• Drive early risk identification and mitigation planning.
• Support customer, vendor, and management reviews whenrequired.

Qualifications

Required Qualifications

• BS/MS in Electrical Engineering or related field.
• 8–12 years of ASIC Physical Design experience.
• Multiple successfultapeoutsin advanced technology nodes.
• Strong experience owning implementation from RTL handoff through GDS signoff.
• Experience leading projects, reviewing deliverables, and coordinating work across multiple stakeholders.
• Floorplanning& Hierarchical Planning
• Power Planning
• Placement & Optimization
• Routing & Signal Integrity
• STA & Timing Closure
• ECO Methodologies
• MCMM Flows
• Power Optimization
• Physical Verification Expertise (Must Have)
• Strong hands-on experience with:
• Calibre
• IC Validator (ICV)
• DRC
• LVS
• ERC
• Density Closure
• Physical Signoff
• Ability to independently debug and resolve complex signoff issues.

Preferred Qualifications

• Experience managing or mentoring junior engineers, contractors, or external vendors.
• StrongTcland Python scripting skills.
• Experience developing implementation methodologies and signoff frameworks.
• Experience with advanced nodes (7nm/5nm/3nm and below).
• Familiarity with low-power implementation and UPF flows.
• Experience with package-awarefloorplanningand bump planning.

Additional Information

All your information will be kept confidential according to EEO guidelines.

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