Physical Design Lead

Mulya Technologies; Ernakulam; On-site; INR 4,500,000 - 6,500,000; Full time

Job summary

Mulya Technologies is seeking a senior Physical Design Lead in Kochi with 11+ years of hands-on experience to lead a 10+ engineer team. The role emphasizes top-level integration, sign-off, floorplanning, power grid understanding, and front-line customer interaction across multiple projects.

Proficiency with Cadence Innovus, Fusion Compiler, Primetime, and Redhawk/EMIR is required. This is a high-responsibility role based in Kerala with opportunities to drive critical silicon outcomes.

Qualifications

• 11+ years’ experience in physical design
• Able to technically lead a team of 10+ engineers
• Strong leadership qualities and escalation management
• Customer-facing project and interaction management

Responsibilities

• Lead development organization to successful delivery of outcomes
• Guide teams to improve code quality, maintainability, security, and scalability
• Oversee daily activities: specs, interfaces, new feature launches and certifications
• Manage top-level integration, sign-off, and power/grid design efforts

Skills

Team leadership

Customer front facing

Floorplanning

Power grid understanding

Scripting

Lead delivery

Tools

Cadence Innovus

Synopsys Fusion Compiler

Primetime

RedHawk

EMIR tools

Job description

Among. The top 4 IT companies, in India ranked by market capitalization and revenue

Bangalore /Hyderabad/Kochi

Physical Design :

Job Description:

At least 11+ years’ experience Able to technically lead team of 10+ engineers, manage multiple customers interaction and projects. Strong leadership quality and able to build and manage team and manage all kind of escalation . Customer front facing .

Lead development organization to successful delivery of outcomes.

Lead teams and other stakeholders to set goals for improving code quality, maintainability, security, scalability, integration and monitor progress.

Lead management and teams through daily activities – specifications, certification, interface, new feature launch and other activities.

Technical requirements:

( 7nm and below exposure, preferred 3nm)

Must have hands-on experience on a complex (SOC/subsystems/SWRPs) implementation of place and route (floorplan to postroute).

strong understanding in PG/floorplan and physical design flows and methodologies,

STA , timing analysis, constraints cleanup and generation, Timing optimization

VCLP, Low power design optimization, UPF/CPF implementation, LEC/FEV implementation and debug

Top level implementation and integration , Signoff

Strong scripting skills in Innovus-Tcl, and Python/Perl(optional).

Top-down floor planning / Partitioning and development of Power Grid understanding is a must.

Tools: Cadence- innovus, synopsys- Fusion compiler, - expert level, Primetime for timing analysis, ansys - redhawk and EMIR tools

skills

pnr

floorplanning

"physical verification"

HPC

"low power design"

"package design"

soc

Innovus

tempus

3nm

VCLP

UPF

CPF

"fusion compiler" / FC

Primetime

redhawk

Contact

[e-mail]

Mulya Technologies

"Mining the Knowledge Community