Physical Design_Pune_CHN

Neurealm; Chennai District; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Neurealm is seeking a highly skilled Physical Design Engineer with deep experience in floor-planning, CTS (Clock Tree Synthesis), power routing, place and route, timing closure, DRC (Design Rule Checking), and LVS (Layout vs. Schematic).

If you are passionate about tackling complex challenges in physical design and possess strong problem-solving and communication skills, we invite you to be part of our dynamic team in Bangalore/Kochi/Chennai/Pune.

Qualifications

• BE/ME or BTech/MTech in Electrical Engineering or related field.
• 3–9 years of experience in physical design.
• Experience with floor-planning, CTS, power routing, place and route, timing closure, DRC and LVS.

Responsibilities

• Execute floor-planning, CTS, power routing, place and route, timing closure, DRC, and LVS for block-level and top-level designs.
• Conduct static timing analysis and implement appropriate fixes.
• Collaborate closely with cross-functional teams, including mentoring and supporting junior engineers.
• Demonstrate the ability to work on designs without a customer flow if required.
• Contribute to the overall success of the team by actively participating in problem-solving and maintaining effective communication within the team.

Skills

Floor-planning

CTS

Power routing

Place and route

Timing closure

DRC

LVS

Static timing analysis

Innovus

Tempus

14nm node

Mentoring juniors

Education

BE/ME or BTech/MTech in Electrical Engineering or related field

Tools

Innovus

Tempus

Job description

Physical Design - Job Description:

Neurealm is looking for a highly skilled Physical Design Engineer with significant experience in floor-planning, CTS (Clock Tree Synthesis), power routing, place and route, timing closure, DRC (Design Rule Checking), and LVS (Layout vs. Schematic). If you are passionate about tackling complex challenges in physical design and possess strong problem-solving and communication skills, we invite you to be part of our dynamic team in Bangalore/Kochi/Chennai/Pune.

Job Posted On

06-08-2026 12:49:25

Job Code

Job_304582

Experience Required

3 - 9 years

Location

• Chennai, Tamil Nadu, India (WAC_007)

Job Summary

Neurealm is looking for a highly skilled Physical Design Engineer with significant experience in floor-planning, CTS (Clock Tree Synthesis), power routing, place and route, timing closure, DRC (Design Rule Checking), and LVS (Layout vs. Schematic). If you are passionate about tackling complex challenges in physical design and possess strong problem-solving and communication skills, we invite you to be part of our dynamic team in Bangalore/Kochi/Chennai/Pune.

Responsibilities

• Execute floor-planning, CTS, power routing, place and route, timing closure, DRC, and LVS for block-level and top-level designs
• Conduct static timing analysis and implement appropriate fixes
• Collaborate closely with cross-functional teams, including mentoring and supporting junior engineers
• Demonstrate the ability to work on designs without a customer flow if required
• Contribute to the overall success of the team by actively participating in problem-solving and maintaining effective communication within the team.

Requirements/Skills

• In-depth experience in floor-planning, CTS, power routing, place and route, timing closure, DRC, and LVS
• Experience in advanced design methodologies and tools like Innovus or tempus
• Familiarity with the latest technology nodes (14nm or lesser)
• Proficiency in static timing analysis and physical verification methodologies
• Strong problem-solving skills and effective communication abilities
• Capability to mentor and work closely with junior engineers

Preferred Skills

• Previous experience working on designs without a customer flow
• Knowledge of advanced design methodologies and tools like Innovus or tempus
• Excellent communication skills with a collaborative and team-oriented mindset

Educational Qualifications

BE/ME or BTech/MTech in Electrical Engineering or related field