Physical Design Engineer Lead

Quest Global; Bengaluru; On-site; INR 800,000 - 1,200,000; Full time

Job summary

Quest Global, located in Bengaluru, Karnataka, is looking for qualified engineers with expertise in Physical aware Synthesis and a strong background in semiconductor technology. Candidates should have the ability to lead teams of junior engineers and demonstrate a comprehensive understanding of Density, Congestion, and Timing issues.

The position involves significant responsibilities including the management of design reviews and improvements at lower tech nodes.

Qualifications

• Experience in Physical aware Synthesis using FC.
• Good at PnR-Floorplan/Macro placement.
• Understanding of Density/Congestion/Timing issues.
• Experience with EM/IR analysis and fixes.
• Participated in at least 2-3 tape-outs.
• Good communication skills.

Responsibilities

• Experience in Physical aware Synthesis using FC.
• Good at PnR-Floorplan/Macro placement.
• Working with Util/area reduction experiments.
• Understanding and fixing DRCs at lower technology nodes.
• Lead junior engineers in projects.

Job description

Company Overview

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Key Responsibilities

• Experience in Physical aware Synthesis using FC
• Good at PnR-Floorplan/Macro placement (200-500 count), hold on BaseDRC review, analysis/fixing
• Working experience on Util/area reduction experiments, good understanding of Density/Congestion/Timing issues and fixes on lower tech nodes (<5nm)
• EM/IR understanding and fixes
• PV closure – Good experience in understanding and fixing the DRCs at lower technology node is mandatory.
• Participated in at least 2-3 tape-outs in lower technology node
• Complete understanding of STA analysis and ECO cycle
• Good communication skills
• Prior experience in leading 4-5 junior Engineers