Physical Design Engineer - ASIC Implementation

Google India Pvt Ltd; Bengaluru; On-site; INR 1,500,000 - 3,200,000; Full time

Job summary

Google India Pvt Ltd in Bengaluru is seeking a mid-level Physical Design and Implementation Engineer to own block- or subsystem-level ASIC RTL2GDS implementations for GPUs, focusing on power, performance, and area.

You will collaborate with RTL, DFT and Foundation IP teams, push AI-driven workflows to boost productivity, and drive QoR improvements across the Tensor SOC.

Qualifications

• Bachelor's degree in EE/CE/CS or related field with 4 years of physical design experience.
• Experience with ASIC RTL to GDSII and QoR assessment.
• Ability to work with RTL, DFT and IP teams.
• Mid-level experience in hardware design and verification.

Responsibilities

• Develop ASIC RTL2GDS implementation for GPU Tensor SOC.
• Manage block and full-chip physical implementation and QoR (power, timing, area).
• Signoff convergence including STA, PDV, IR and EM.
• Optimize power, performance and area with AI-driven design tools.
• Collaborate with RTL/DFT/Foundation IP teams.
• Support time-to-market improvements via design flows.

Skills

ASIC design

PPA optimization

Power optimization

Performance optimization

Digital design

Team collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science

Master's or PhD in Electrical Engineering, Computer Engineering or Computer Science (computer architecture focus)

Job description

Physical Design and Implementation Engineer, Silicon Engineering

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience in physical design with two or more chip tape outs.

Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience in power, performance and area optimization. Experience in high performance designs (CPUs, GPUs, DSPs or other compute etc.).

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Physical Design Engineer in the GPU Implementation team, you will own block or subsystem implementation of complex logic blocks with special focus on optimizing Power, Performance and Area (PPA). You will be working closely with the RTL, DFT and Foundation IP teams to improve PPA, deploy AI workflows to improve productivity, time to market and PPA.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Physical Design Engineer in the GPU Implementation team, you will own block or subsystem implementation of complex logic blocks with special focus on optimizing Power, Performance and Area (PPA). You will be working closely with the RTL, DFT and Foundation IP teams to improve PPA, deploy AI workflows to improve productivity, time to market and PPA.

Responsibilities

• Develop all aspects of ASIC RTL2GDS implementation for Graphics Processing Unit (GPU) for the Tensor SOC.
• Manage block and full-chip level physical implementation and Quality of Results (QoR) (power, timing, area).
• Signoff convergence inclusing Static Timing Analysis (STA), Physical Design Verification (PDV), IR and EM (Electo-Migration).
• Optimize power, performance and area to achieve performance and cost.
• Reduce time to market and improve PPA through deployment of Artifical Intelligence (AI) physical design tools and workflows.
• Manage block and full-chip level physical implementation and Quality of Results (QoR) (power, timing, area).
• Manage block and full-chip level physical implementation and Quality of Results (QoR) (power, timing, area).

Experience Level Mid Level