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nHRMS is seeking a Physical Design Engineer to join our VLSI backend team. You will work on floorplanning, placement, and routing for design blocks, contributing to timing and area closure from RTL handoff through tapeout.
Key responsibilities include floorplanning, power planning, placement, clock tree synthesis, routing, DRC/LVS signoff, timing closure at block level, physical verification, ECO implementation, and collaboration with STA, DFT and RTL teams for seamless full-chip integration.
We are hiring a Physical Design Engineer to join our VLSI backend team. You will work on floorplanning, placement, and routing for design blocks, contributing to timing and area closure from RTL handoff through tapeout.