Physical Design Engineer - Hyderabad

n Human Resources & Management Systems [ nHRMS ]; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

n HRMS is seeking a Physical Design Engineer for its VLSI backend team in Hyderabad. The role involves floorplanning, placement, and routing for design blocks, driving timing and area closure from RTL handoff through tapeout.

Responsibilities include floorplanning, power planning, clock tree synthesis, signoff checks, and collaboration with STA/DFT/RTL teams for block-level closure, with opportunities to support full-chip integration as needed.

Qualifications

• 4-5 years of hands-on experience in physical design (floorplan through signoff).
• Solid understanding of STA fundamentals and DRC/LVS signoff flows.

Responsibilities

• Floorplanning, power planning, placement, and clock tree synthesis.
• Routing, DRC/LVS clean-up, and signoff checks.
• Timing closure at block level across corners and modes.
• Physical verification and ECO implementation.
• Collaborate with STA, DFT, and RTL design teams on block-level closure.
• Support full-chip integration activities as needed.

Skills

Floorplanning

Power planning

Placement

Clock tree synthesis

Routing

DRC/LVS signoff

Tools

ICC2/Innovus

Job description

Job Description

We are hiring a Physical Design Engineer to join our VLSI backend team. You will work on floorplanning, placement, and routing for design blocks, contributing to timing and area closure from RTL handoff through tapeout.

Key Responsibilities

• Floorplanning, power planning, placement, and clock tree synthesis
• Routing, DRC/LVS clean-up, and signoff checks
• Timing closure at block level across corners and modes
• Physical verification and ECO implementation
• Collaborate with STA, DFT, and RTL design teams on block-level closure
• Support full-chip integration activities as needed

Requirements

• 4-5 years of hands-on experience in physical design (floorplan through signoff)
• Proficiency with industry-standard P&R tools (ICC2/Innovus or equivalent)
• Solid understanding of STA fundamentals and DRC/LVS signoff flows