PERC Rule Deck Development Engineer

Intel Corporation; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Intel Corporation in Bengaluru is seeking a PERC Runset Development Engineer to develop and validate PERC rule decks, collaborating with the PDK team and foundry to ensure design compliance.

You will develop, validate, and maintain PERC rules for electrical reliability, integrate flows across Calibre PERC, Cadence Pegasus, and Synopsys tools, and automate checks with Python/Tcl scripting.

Qualifications

• Experience with PERC rule development (Calibre PERC preferred).
• Knowledge of ESD, latch-up and reliability verification.
• Familiarity with SVRF, TVF, Python or Tcl scripting.
• Strong debugging and problem-solving skills.
• Knowledge of Linux and scripting (Python/Shell/Tcl) is desirable.
• Experience with advanced technology nodes is an advantage.

Responsibilities

• Develop, validate, and maintain complex PERC rule decks to identify electrical reliability violations.
• Develop and optimize verification flows across Calibre PERC, Cadence Pegasus, and Synopsys tools.
• Collaborate with Device Physicists, Process Integration Engineers, and Analog Designers to translate reliability requirements into programmable rules.
• Provide expert-level debugging support to design teams for PERC violations.
• Develop scripts to automate execution, reporting, and tracking of reliability checks.
• Maintain detailed documentation of reliability check-sets and guidelines for designers.

Skills

PERC rule development

ESD reliability verification

SVRF/TVF scripting

Python/Tcl scripting

Linux scripting

Debugging

Multi-tool verification flows

Team collaboration

Advanced technology nodes

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree in Electrical/Computer Engineering

PhD in EE/CE or related field

Tools

Calibre PERC

Cadence Pegasus

Synopsys tools

Job description

Job Details:

Job Description:

We are looking for a PERC Runset Development Engineer to develop and Validate PERC (Programmable Electrical Rule Checker) rule decks. The role involves working closely with PDK Team and foundry to implement PERC and ensure design compliance.

• Rule Development: Develop, validate, and maintain complex PERC rule decks to identify electrical reliability violations (e.g., ESD paths, current density, voltage stress, and floating gates).
• Multi-Tool Integration: Develop and optimize verification flows across multiple EDA environments, ensuring consistency in results between Calibre PERC( preferred), Cadence Pegasus, and Synopsys tools.
• Cross-Functional Collaboration: Work closely with Device Physicists, Process Integration Engineers, and Analog Designers to translate reliability requirements into programmable rules.
• Debug and Analysis: Provide expert-level support to design teams in debugging PERC violations, distinguishing between true reliability risks and tool-induced false positives.
• Automation: Develop scripts (Python, SKILL, Tcl, or Perl) to automate the execution, reporting, and tracking of reliability checks across different design versions.
• Documentation: Maintain detailed documentation of reliability check-sets and create guidelines for designers to implement correct-by-construction layouts.

Qualifications:

Required Skills:

• Experience with PERC rule development (preferably using Calibre PERC).
• Knowledge of ESD, latch-up and reliability verification.
• Familiarity with SVRF, TVF, Python or Tcl scripting.
• Strong debugging and problem-solving skills.
• Knowledge of Linux and scripting (Python/Shell/Tcl) is desirable.
• Experience with advanced technology nodes is an advantage.
• Team player and be able to work with global teams.

Preferred Qualifications:

• Bachelor’s degree with 10+ years of experience, OR
• Master’s degree with 8+ years of experience, OR
• PhD degree with 2+ years of experience in Electrical Engineering, Computer Engineering, Electronics or related field; semiconductor industry experience.
• Basic AI experience is an added skill.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during your hiring process, please report this immediately to your recruiter.