LVS Runset Development Engineer

Intel Technology India Pvt Ltd

Bengaluru

On-site

INR 3,500,000 - 7,000,000

Full time

6 days ago
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Job summary

Intel Technology India Pvt Ltd in Bengaluru is seeking an experienced LVS Runset Development Engineer to develop and validate LVS rule decks, and to ensure design compliance in collaboration with PDK teams and foundries.

The role emphasizes rule development, multi-tool integration (ICV/Calibre/Pegasus), debugging, automation, and thorough documentation, with a strong preference for senior candidates and global teamwork.

Qualifications

  • Experience with LVS runset development.
  • Familiarity with SVRF, TVF, Python or Tcl scripting.
  • Strong debugging and problem-solving skills.
  • Knowledge of Linux and scripting (Python/Shell/Tcl).
  • Experience with advanced technology nodes is an advantage.

Responsibilities

  • Develop and QA support of LVS/extraction runsets for Intel's process.
  • Develop and optimize verification flows across EDA environments (ICV, Calibre, Pegasus).
  • Collaborate with Device Physicists, Process Integration Engineers, and Analog Designers.
  • Provide expert-level debugging support for LVS issues.
  • Automate workflows with Python, Tcl or Perl scripts.
  • Maintain documentation and guidelines for correct-by-construction layouts.

Skills

LVS runset development
SVRF/TVF scripting
Python scripting
Tcl scripting
Debugging skills

Education

Bachelor's degree + 10+ years experience
Master's degree + 8+ years experience
PhD + 2+ years experience

Tools

Linux
ICV
Calibre
Pegasus

Job description

LVS Runset Development Engineer Job Details: Job Description: \"We are looking for a LVS Runset Development Engineer to develop and Validate LVS rule decks. The role involves working closely with PDK Team and foundry to implement LVS runsets and ensure design compliance.

Key Responsibilities
  • Rule Development: Development and QA support of LVS/extraction runset for Intel's process.
  • Multi-Tool Integration: Develop and optimize verification flows across multiple EDA environments, ensuring consistency in results between ICV, Calibre and Pegasus tools.
  • Cross-Functional Collaboration: Work closely with Device Physicists, Process Integration Engineers, and Analog Designers.
  • Debug and Analysis: Provide expert-level support to design teams in debugging LVS issues.
  • Automation: Develop scripts (Python, SKILL, Tcl, or Perl) to automate the execution, reporting, and tracking across different design versions.
  • Documentation: Maintain detailed documentation and create guidelines for designers to implement correct-by-construction layouts.
Qualifications
  • Experience with LVS runset development.
  • Familiarity with SVRF, TVF, Python or Tcl scripting.
  • Strong debugging and problem-solving skills.
  • Knowledge of Linux and scripting (Python/Shell/Tcl) is desirable.
  • Experience with advanced technology nodes is an advantage.
  • Team player and be able to work with global teams.
Preferred Qualifications
  • Bachelor's degree with 10+ years of experience, OR
  • Master's degree with 8+ years of experience, OR
  • PhD degree with 2+ years of experience in LVS runset development or related field; semiconductor industry experience.
  • Basic AI experience is an added skill.

Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations:

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation or ordinance.

Position of Trust N/A

Work Model for this Role

This role will require an on-site presence.

* Job posting details (such as work model, location or time type) are subject to change.

* ADDITIONAL INFORMATION:

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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