LVS Runset Development Engineer

Intel Corporation; Bengaluru; On-site; INR 2,000,000 - 3,600,000; Full time

Job summary

Intel Corporation in Bengaluru, India is seeking an experienced LVS Runset Development Engineer to develop and validate LVS rule decks and ensure design compliance across process nodes.

You will collaborate with the PDK team and foundry, integrate multi-tool flows (ICV, Calibre, Pegasus), automate with Python/Tcl, and contribute to documentation and guidelines for designers.

Qualifications

• Experience in LVS runset development and verification.
• Proficiency in SVRF/TVF and scripting languages.
• Strong debugging and problem-solving skills.
• Knowledge of Linux and scripting (Python/Shell/Tcl) is desirable.
• Experience with advanced technology nodes is an advantage.
• Ability to work with global teams.

Responsibilities

• Rule Development: Development and QA support of LVS/extraction runset for Intel's process.
• Multi-Tool Integration: Develop and optimize verification flows across multiple EDA environments.
• Cross-Functional Collaboration: Work with Device Physicists, Process Integration Engineers, and Analog Designers.
• Debug and Analysis: Provide expert-level support to design teams in debugging LVS issues.
• Automation: Develop scripts to automate execution, reporting, and tracking across designs.
• Documentation: Maintain detailed documentation and create guidelines for designers to implement layouts.

Skills

LVS runset development

Python scripting

Tcl scripting

Linux experience

Debugging

Team collaboration

Education

Bachelor's degree (10+ yrs)

Master's degree (8+ yrs)

PhD (2+ yrs)

Tools

SVRF

TVF

ICV

Calibre

Pegasus

Job description

Job Details: Job Description:

We are looking for a LVS Runset Development Engineer to develop and Validate LVS rule decks. The role involves working closely with PDK Team and foundry to implement LVS runsets and ensure design compliance.

Key Responsibilities:

• Rule Development: Development and QA support of LVS/extraction runset for Intel's process.
• Multi-Tool Integration: Develop and optimize verification flows across multiple EDA environments, ensuring consistency in results between ICV, Calibre and Pegasus tools.
• Cross-Functional Collaboration: Work closely with Device Physicists, Process Integration Engineers, and Analog Designers.
• Debug and Analysis: Provide expert-level support to design teams in debugging LVS issues.
• Automation: Develop scripts (Python, SKILL, Tcl, or Perl) to automate the execution, reporting, and tracking across different design versions.
• Documentation: Maintain detailed documentation and create guidelines for designers to implement correct-by-construction layouts.

Qualifications:

Required Skills:

• Experience with LVS runset development.
• Familiarity with SVRF, TVF, Python or Tcl scripting.
• Strong debugging and problem-solving skills.
• Knowledge of Linux and scripting (Python/Shell/Tcl) is desirable.
• Experience with advanced technology nodes is an advantage.
• Team player and be able to work with global teams.

Preferred Qualifications:

• Bachelor's degree with 10+ years of experience, OR
• Master's degree with 8+ years of experience, OR
• PhD degree with 2+ years of experience in LVS runset development or related field; semiconductor industry experience.
• Basic AI experience is an added skill.

Job Type:

Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. Job posting details (such as work model, location or time type) are subject to change. ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during your hiring process, please report this immediately to your recruiter. Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology.

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