LVS Runset Development Engineer

Intel; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

Intel in Bengaluru is seeking an LVS Runset Development Engineer to develop and validate LVS rule decks and ensure design compliance across Intel processes.

The role involves collaborating with PDK teams and foundries, developing automation scripts in Python/Tcl, and providing expert debugging for LVS issues. On-site role with global team interaction is expected.

Qualifications

• Experience in LVS runset development and QA support.
• Familiarity with LVS/extraction runsets and process/design rules.
• Proficient in Python, Tcl, and shell scripting.
• Strong debugging and problem‑solving skills with Linux experience.
• Experience with advanced technology nodes is a plus.

Responsibilities

• Rule Development: Develop and QA LVS/extraction runset for Intel's process.
• Multi-Tool Integration: Optimize verification flows across ICV, Calibre and Pegasus.
• Cross-Functional Collaboration: Work with Device Physicists, Process Integration Engineers, and Analog Designers.
• Debug and Analysis: Provide expert-level support to design teams for LVS issues.
• Automation: Develop scripts to automate execution, reporting, and tracking across design versions.
• Documentation: Maintain docs and guidelines for designers.

Skills

LVS runset development

SVRF/TVF

Python

Tcl scripting

Linux scripting

Debugging

Problem solving

Education

Bachelor's degree with 10+ years experience OR

Master's degree with 8+ years experience

PhD with 2+ years experience in LVS/semiconductor

Tools

ICV

Calibre

Pegasus

Python

Tcl

SVRF/TVF

Job description

Job Details:

Job Description:

"We are looking for a LVS Runset Development Engineer to develop and Validate LVS rule decks. The role involves working closely with PDK Team and foundry to implement LVS runsets and ensure design compliance."

Key Responsibilities:

• Rule Development: Development and QA support of LVS/extraction runset for Intel's process.
• Multi-Tool Integration: Develop and optimize verification flows across multiple EDA environments, ensuring consistency in results between ICV, Calibre and Pegasus tools.
• Cross-Functional Collaboration: Work closely with Device Physicists, Process Integration Engineers, and Analog Designers.
• Debug and Analysis: Provide expert-level support to design teams in debugging LVS issues.
• Automation: Develop scripts (Python, SKILL, Tcl, or Perl) to automate the execution, reporting, and tracking across different design versions.
• Documentation: Maintain detailed documentation and create guidelines for designers to implement correct-by-construction layouts.

Qualifications:

Required Skills:

• Experience with LVS runset development.
• Familiarity with SVRF, TVF, Python or Tcl scripting.
• Strong debugging and problem-solving skills.
• Knowledge of Linux and scripting (Python/Shell/Tcl) is desirable.
• Experience with advanced technology nodes is an advantage.
• Team player and be able to work with global teams.

Preferred Qualifications:

• Bachelor's degree with 10+ years of experience, OR
• Master's degree with 8+ years of experience, OR
• PhD degree with 2+ years of experience in LVS runset development or related field; semiconductor industry experience.
• Basic AI experience is an added skill.

Job Type: Experienced Hire

Shift: Shift 1 (India)

Primary Location: India, Bangalore

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.