Lead PERC Rule Deck Development Engineer

NXP Semiconductors; India; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

NXP Semiconductors in India seeks a Lead PERC Rule Developer to drive PERC methodology, rule development, and flow enablement for ESD, latch-up, power-domain, and reliability verification. You will collaborate with design, CAD, technology and verification teams across sites and time zones to deliver robust physical verification solutions.

The role requires deep CMOS/FinFET knowledge, hands-on Calibre PERC/LVS, and scripting in TCL, Python, and SVRF.

Qualifications

• BTech/BE/ME/MTech in Electronics & Communication or related field with 10+ years' industry experience.
• Strong hands-on expertise in PERC rule development, debugging, validation in production design.
• Good understanding of ESD fundamentals (HBM, CDM) and system-level ESD models.
• Proficiency in TCL, Perl, Python, SKILL, and TVF/SVRF for automation.
• Solid CMOS basics including advanced-node and FinFET, plus analog/mixed-signal flows.
• Experience with Calibre PERC/LVS and Cadence Virtuoso; knowledge of Quantus or similar.

Responsibilities

• Lead development, validation, and release of Calibre PERC rule decks for ESD and reliability.
• Translate requirements into scalable PERC checks and reusable verification methods.
• Drive PERC flow enablement across IP to SoC design stages with LVS integration.
• Debug complex PERC/LVS issues with cross-functional teams; provide root-cause analysis.
• Develop automation scripts, regression suites, and reporting utilities.
• Partner with analog, AMS, CAD, product teams to define verification plans.
• Establish best practices for rule coding, test cases, and version control.
• Support IP readiness, tapeout prep, and customer sign-off readiness.
• Mentor junior engineers to build PERC and physical verification competency.

Skills

PERC rule development

TCL

Perl

Python

SKILL

TVF/SVRF

LVS

Calibre PERC/LVS

Cadence Virtuoso

AMS verification

RC extraction

Transistor-level extraction

CMOS fundamentals

FinFET tech

layout effects

Education

BTech/BE/ME/MTech in Electronics & Communication or related

Tools

Cadence Virtuoso

Siemens Calibre PERC/LVS

Job description

Summary

The Lead PERC Rule Developer will drive PERC methodology, rule development, and flow enablement for ESD, latch-up, power-domain, connectivity, and reliability-related verification. The role requires strong hands‑on expertise in Calibre LVS/PERC, CMOS and FinFET fundamentals, analog/mixed‑signal design flows, and close collaboration with cross‑functional design, CAD, technology, and verification teams across multiple sites and time zones.

Job Qualification

BTech/BE/ME/MTech in Electronics & Communication, Electrical Engineering, Microelectronics, VLSI, or a related discipline with at least 10 years of relevant industry experience. Strong hands‑on expertise in PERC (Programmable Electrical Rule Check) rule development, debugging, validation, and deployment in production design environments. Good understanding of ESD fundamentals, including HBM, CDM, and system‑level ESD models, along with modern ESD protection techniques and verification methodologies. Proficiency in scripting and programming languages such as TCL, Perl, Python, SKILL, and TVF/SVRF for rule automation, flow development, debug utilities, and regression infrastructure. Good understanding of analog and analog mixed‑signal design flows, including schematic, layout, extraction, simulation, and signoff dependencies. Solid understanding of CMOS fundamentals, including advanced‑node and FinFET technologies, device behavior, layout effects, and reliability considerations. Experience with EDA tools such as Cadence Virtuoso, Siemens Calibre PERC/LVS. Knowledge of Cadence Quantus or equivalent extraction and verification platforms is a plus. Experience in leading physical verification flows across IP, block, subsystem, and SoC levels throughout different stages of the design cycle. Familiarity with AMS verification and transistor‑level RC extraction is an advantage. Experience working with cross‑functional design, CAD, technology foundry/interface, and product teams across different time zones. Strong interpersonal skills, clear communication style, ownership mindset, and ability to work effectively as a team player and technical lead.

Job Responsibilities

• Lead development, enhancement, validation, and release of Calibre PERC rule decks for ESD, latch‑up, power‑domain, connectivity, and reliability verification requirements.
• Translate technology, product, and design signoff requirements into scalable, maintainable PERC checks and reusable verification methodologies.
• Drive PERC flow enablement across IP, block, subsystem, and SoC design stages, ensuring consistent integration with LVS, extraction, and overall physical verification signoff flows.
• Debug complex PERC/LVS issues in collaboration with design, layout, CAD, and technology teams; provide clear root‑cause analysis and actionable closure recommendations.
• Develop automation scripts, regression suites, quality checks, and reporting utilities to improve rule development efficiency, release quality, and traceability.
• Partner with analog, AMS, CAD, product, and technology stakeholders to define verification requirements, acceptance criteria, and deployment plans for new or enhanced checks.
• Establish best practices for rule coding, validation, test‑case creation, documentation, version control, and release readiness.
• Support design teams during key milestones such as IP readiness, MPW/FDIP development, tapeout preparation, and customer sign‑off readiness.
• Monitor rule deck quality, resolve priority issues, and provide timely status reporting to stakeholders and management.
• Mentor junior engineers and help build PERC, ESD, and physical verification competency within the team.

Preferred / Additional Experience

• Exposure to AMS verification, reliability verification, or custom analog signoff flows.
• Hands‑on experience with transistor‑level extraction, post‑layout verification, or RC‑aware debug.
• Experience defining methodology roadmaps, reusable verification platforms, or productivity automation for large design organizations.

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