Packaging Lead FOL

Tata Electronics (TEPL); Assam; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Tata Electronics (TEPL) is seeking an experienced Front-of-Line (FOL) Lead to own and optimize IC assembly/process steps up to EOL handoff in a high-volume OSAT environment.

The candidate will bring deep process expertise across wafer bump/RDL, wafer thinning, dicing, die prep, die attach, wire bond/flip-chip attach, underfill, molding, singulation, and pre-test/readiness, driving yield, cost, cycle time, and reliability improvements while ensuring stable HVM at OSATs.

Qualifications

• Must have deep process expertise across wafer bump/RDL, wafer thinning dicing, die prep, die attach, wire bond/flip-chip attach, underfill, molding, singulation, and pre-test/readiness.
• Experience with APQP/PPAP, SPC/MSA/DOE, FMEA, 8D, reliability (JEDEC/AEC).
• Strong understanding of assembly/process flows and failure modes (delamination, bond lift, die crack, BLR/CLR).

Responsibilities

• Own end-to-end FOL process flows for packages (QFN/QFP, BGA/FCBGA, WLCSP, SIP/POP).
• Define, optimize, and maintain process windows, golden parameters, and control plans.
• Manage COM levers: materials usage, rework, tool life, consumables, and setup optimization.
• Create package build plans, control plans, and PFMEA for new products/packages.
• Lead engineering builds, pilot runs, correlation plans, and ramp-to-HVM with stable yields and CPK.

Skills

FOL lead expertise

IC packaging knowledge

Wafer bump/RDL

Die prep/attach

Wire bond/flip-chip attach

Underfill/molding/singulation

Yields/CPK improvement

Quality ownership

Education

Bachelor's/Master's in Materials, Mechanical, Electronics, Packaging, or Manufacturing Engineering

Job description

Responsibilities

We are seeking an experienced Front-of-Line (FOL) Lead to own and optimize IC assembly/process steps up to EOL handoff in a high-volume OSAT environment. The ideal candidate brings deep process expertise across wafer bump/RDL, wafer thinning dicing, die prep, die attach, wire bond/flip-chip attach, underfill, molding, singulation, and pre-test/readiness, driving yield, cost, cycle time, and reliability improvements while ensuring stable HVM at OSATs.

Key Responsibilities

• Own end-to-end FOL process flows for assigned packages (e.g., QFN/QFP, BGA/FCBGA, WLCSP, SIP/POP).
• Define, optimize, and maintain process windows, golden parameters, and control plans for:
  • Wafer-level: RDL, UBM, bumping (Cu pillar/SnAg), wafer thinning, WLCSP passivation, dicing/saw.
  • Die prep/attach: die singulation, pick/place, epoxy/DAF attach, eutectic/Ag-sinter, FC attach.
  • Interconnect: wire bond (Au/Cu/Al), stud bumping, flip-chip reflow; underfill/edge-bonding.
  • Encapsulation singulation: transfer mold/compression mold, post-mold cure, saw/laser singulation.
• Own cost of manufacturing (COM) levers: materials usage (epoxy, underfill, mold compound), rework, tool life, consumables, and setup optimization
• Create package build plans, control plans, and risk assessments (PFMEA) for new products/packages.
• Lead engineering builds, pilot runs, correlation plans, and ramp-to-HVM with stable yields and CPK.

Essential Attributes

• Proven track record in advanced IC packaging: Wirebond, Flip-Chip, WLCSP, SiP, Fan-Out, or 2.5D/3D.
• Deep hands-on experience with APQP/PPAP, SPC/MSA/DOE, FMEA, 8D, and reliability (JEDEC/AEC).
• Strong understanding of assembly/process flows and failure modes (e.g., delamination, bond lift, die crack, BLR/CLR, substrate warpage).
• Customer-facing quality ownership, including escalation handling and audit leadership.
• Experience with automotive (IATF 16949) or AEC-Q100/104 qualification.

Qualifications

• Bachelor's/Master's in Materials, Mechanical, Electronics, Packaging, or Manufacturing Engineering (or related).

Responsibilities

We are seeking an experienced Front-of-Line (FOL) Lead to own and optimize IC assembly/process steps up to EOL handoff in a high-volume OSAT environment. The ideal candidate brings deep process expertise across wafer bump/RDL, wafer thinning dicing, die prep, die attach, wire bond/flip-chip attach, underfill, molding, singulation, and pre-test/readiness, driving yield, cost, cycle time, and reliability improvements while ensuring stable HVM at OSATs.

Key Responsibilities

• Own end-to-end FOL process flows for assigned packages (e.g., QFN/QFP, BGA/FCBGA, WLCSP, SIP/POP).
• Define, optimize, and maintain process windows, golden parameters, and control plans for:
  • Wafer-level: RDL, UBM, bumping (Cu pillar/SnAg), wafer thinning, WLCSP passivation, dicing/saw.
  • Die prep/attach: die singulation, pick/place, epoxy/DAF attach, eutectic/Ag-sinter, FC attach.
  • Interconnect: wire bond (Au/Cu/Al), stud bumping, flip-chip reflow; underfill/edge-bonding.
  • Encapsulation singulation: transfer mold/compression mold, post-mold cure, saw/laser singulation.
• Own cost of manufacturing (COM) levers: materials usage (epoxy, underfill, mold compound), rework, tool life, consumables, and setup optimization
• Create package build plans, control plans, and risk assessments (PFMEA) for new products/packages.
• Lead engineering builds, pilot runs, correlation plans, and ramp-to-HVM with stable yields and CPK.

Essential Attributes

• Proven track record in advanced IC packaging: Wirebond, Flip-Chip, WLCSP, SiP, Fan-Out, or 2.5D/3D.
• Deep hands-on experience with APQP/PPAP, SPC/MSA/DOE, FMEA, 8D, and reliability (JEDEC/AEC).
• Strong understanding of assembly/process flows and failure modes (e.g., delamination, bond lift, die crack, BLR/CLR, substrate warpage).
• Customer-facing quality ownership, including escalation handling and audit leadership.
• Experience with automotive (IATF 16949) or AEC-Q100/104 qualification.

Qualifications

• Bachelor's/Master's in Materials, Mechanical, Electronics, Packaging, or Manufacturing Engineering (or related).