NoC Design Lead

Larsen & Toubro; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

LTSCT — L&T Semiconductor Technologies Limited in Bengaluru invites two NoC Design Leads to own the stacked Network-on-Chip that forms the data backbone of xPU, delivering 12 TB/s cross-section bandwidth.

You will architect coherency, routing, QoS, and bandwidth allocation across BFOS arrays, UCIe links, HBM controllers, SRAM banks, and host interfaces, driving RTL and micro-architecture work through to integration.

Qualifications

• 10+ years designing on-chip interconnects/NoCs or coherent fabrics.
• Deep understanding of NoC topologies, routing, QoS.
• Cache-coherence protocols (MESI/MOESI) knowledge.
• RTL design (SystemVerilog) for routers and arbiters.
• Cycle-accurate simulation and performance modeling.
• Experience with NoC generators/IP and integration.
• Familiarity with HBM and UCIe traffic characteristics.
• Python/Perl scripting for automation and verification support.
• Strong documentation and leadership.
• Cross-team collaboration and architectural reviews.

Responsibilities

• Own the stacked 4-plane NoC delivering 12 TB/s bandwidth across endpoints.
• Define topology, routing, virtual channels, and arbitration.
• Design QoS and bandwidth allocation across BFOS, SRAM banks, HBM, UCIe, and host.
• Own on-chip coherency protocol and its interaction with SRAM/HBM/host.
• Drive micro-architecture, RTL, and integration of routers, buffers, and CDCs.
• Model latency and congestion via cycle-accurate simulation and traffic generators.
• Collaborate on floorplan-aware NoC partitioning with PD and DFT teams.
• Define QoR metrics, mentor engineers, and participate in reviews.

Skills

NoC architectures

RTL SystemVerilog

Performance modeling

Cycle-accurate simulation

Cache coherence protocols

Traffic analysis

HDL verification

Leadership

Cross-team collaboration

Python scripting

Education

M.Tech/MS in EE/ECE/CS

B.E./B.Tech

Tools

NoC generators

UCIe

HBM

Job description

NoC Design Lead (×2 openings)

Location: Bangalore, India | Company: LTSCT — L&T Semiconductor Technologies Limited

Reporting To: Chandra — Senior Architect, DC HW Systems | Experience: 10+ years (mandatory)

Role Summary

We are hiring two NoC Design Leads to own the stacked Network-on-Chip that forms the data backbone of xPU — 4 physical planes delivering 12 TB/s cross-section bandwidth. You will architect and implement coherency, routing, QoS, and bandwidth allocation across the BFOS arrays, banked SRAM, HBM controllers, UCIe links, and the host interface. This role is central to sustaining the extreme bandwidth and latency targets the compute architecture demands.

Key Responsibilities

• Architect and implement the 4-plane stacked NoC delivering 12 TB/s cross-section bandwidth across all on-chip and off-chip endpoints.
• Define topology, routing algorithms, virtual channels, and arbitration to guarantee deadlock-free, high-throughput data movement.
• Design QoS and bandwidth-allocation mechanisms balancing traffic between dual BFOS arrays, 512 SRAM banks, HBM controllers, UCIe, and host.
• Own the on-chip coherency protocol and its interaction with SRAM, HBM, and the host-interface coherency layer.
• Drive micro-architecture, RTL, and integration of routers, network interfaces, buffers, and clock-domain crossings.
• Model and analyze latency, bandwidth, and congestion via cycle-accurate simulation and traffic generators; close performance targets.
• Collaborate with PD on floorplan-aware NoC partitioning across the 4 physical planes and with DFT/verification on coverage.
• Define QoR/performance metrics, mentor engineers, and represent NoC in architecture and integration reviews.

Required Skills & Experience

• 10+ years designing on-chip interconnects/NoCs or coherent fabrics for high-performance SoCs.
• Deep understanding of NoC topologies (mesh, torus, crossbar, stacked/multi-plane), routing, flow control, and QoS.
• Strong grasp of cache-coherency protocols (MESI/MOESI-class, directory-based) and memory-consistency models.
• Expertise in RTL design (SystemVerilog) of routers, arbiters, buffers, and asynchronous/CDC interfaces.
• Hands-on performance modeling and analysis — cycle-accurate simulation, traffic modeling, bandwidth/latency closure.
• Experience with commercial or in-house NoC generators/IP and their integration methodology.
• Familiarity with high-bandwidth memory (HBM) and chiplet interconnect (UCIe) traffic characteristics.
• Proficiency in scripting (Python/Perl) for performance analysis and verification support.
• Strong micro-architecture, specification, and documentation skills.
• Demonstrated technical leadership and cross-team collaboration.

Preferred Qualifications

• Experience with multi-plane or 3D-stacked NoC architectures.
• Background in AI accelerator or GPU dataflow interconnects.
• Familiarity with formal verification of coherency/deadlock properties.
• M.Tech/MS in EE/ECE/CS or equivalent.