MTS DRAM ASIC Architect

Micron Technology, Inc; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Benefits offered by this job

Medical, dental, vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. in Bengaluru seeks an MTS DRAM ASIC Architect to define next‑generation DRAM+logic‑die architectures that enable higher performance and power efficiency across LPDDR, DDR, and HBM platforms.

You will collaborate with DRAM design, ASIC architecture, packaging, process technology, product engineering, validation, firmware, and system teams to deliver scalable memory solutions.

Qualifications

• 5+ years in semiconductor architecture, design, or system engineering.
• Experience in DRAM architecture, memory subsystem architecture, or ASIC/SoC architecture.
• Knowledge of DRAM command flows, timing, and memory subsystems.
• Exposure to high-speed I/O, PHY architectures, clocking, SI/PI considerations.

Responsibilities

• Define next-generation DRAM + logic-die architectures for LPDDR, DDR, and HBM.
• Perform architectural trade-off analysis across area, power, latency, and reliability.
• Architect high-performance interfaces between DRAM die and logic die.
• Collaborate across DRAM design, ASIC, packaging, process tech, validation, and firmware teams.
• Identify opportunities to leverage CMOS logic-die capabilities to differentiate products.

Skills

Cross-functional leadership

Analytical thinking

Problem solving

Architectural trade-offs

Education

BS in Electrical/Computer Engineering

MS or PhD welcomed

Job description

MTS DRAM ASIC Architect

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Role Overview

Micron is seeking an experienced architect to drive the definition of next-generation DRAM products incorporating advanced CMOS-based logic die technologies. This role will help define how future DRAM products leverage advanced CMOS logic die technologies to enable higher levels of integration, observability, reliability, power efficiency, security, and system differentiation beyond what is achievable in conventional DRAM-only implementations. The architect will define architectures that leverages advanced logic die capabilities to complement and enhance DRAM functionality across LPDDR, DDR, HBM and future heterogeneous memory solutions.

The successful candidate will architect I/O, reliability, manageability, interface, test and system‑enhancement functions. The role requires strong collaboration across DRAM design, ASIC architecture, packaging, process technology, product engineering, validation, firmware, and system architecture teams.

Key Responsibilities

• Define next‑generation DRAM + logic‑die architectures, including functional partitioning between DRAM arrays, peripheral circuitry, and advanced CMOS logic die platforms – to optimize performance, power, cost, reliability, and product differentiation.
• Identify and evaluate system, interface, reliability, test, management, and control functions that may benefit from advanced logic‑die implementations; perform architectural trade‑off analysis covering area, power, latency, yield, testability, reliability, and product scalability.
• Define scalable CMOS logic‑die architectures and subsystem solutions using a combination of custom, semi‑custom, and standard IP solutions.
• Architect high‑performance interfaces between DRAM die and logic die, including command, data, clocking, synchronization, test, monitoring, and management paths.
• Identify emerging opportunities and influence roadmaps for advanced memory system capabilities.

Minimum Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related discipline with 5+ years of experience in semiconductor architecture, design, or system engineering.
• Experience in one or more of the following areas: DRAM architecture, memory subsystem architecture, ASIC/SoC architecture.
• Good understanding of DRAM architecture including command flows, timing behavior, bank architecture, refresh management, row hammer mitigation, reliability features, and memory subsystem operation.
• Exposure to high‑speed I/O, PHY architectures, clocking systems, SI/PI considerations, power delivery, thermal design, and/or die‑to‑die interfaces.
• Demonstrated ability to lead cross‑functional technical discussions, develop architectural proposals, and drive trade‑off based decision making.
• Strong analytical and problem‑solving skills.
• Ability to drive architecture trade‑off studies across multiple engineering disciplines.
• Excellent written and verbal communication skills.

Preferred Qualifications

• Experience with DDR5/DDR6, LPDDR5/LPDDR6, HBM, GDDR, or emerging memory technologies with strong understanding of memory protocols, timing architectures, memory training, calibration, and PHY design.
• Experience evaluating architectural tradeoffs across DRAM die, logic die, advanced packaging, and system‑level implementations.
• Experience with die‑to‑die interconnect technologies including TSV‑based architectures, hybrid bonding, 2.5D/3D packaging, stacked‑die systems, and advanced memory integration.
• Strong knowledge of CMOS technologies, semiconductor device fundamentals, analog/mixed‑signal circuit concepts, and memory interface design.
• Understanding of SI/PI, clocking, power delivery, thermal considerations, and heterogeneous integration challenges.
• Experience working with industry standards organizations, customers, or ecosystem partners related to memory technologies.
• Experience with HBM base die architectures, embedded controllers, advanced memory system features, RAS, security, or logic‑die‑based memory products.
• Proven ability to leverage AI‑assisted (vibe) coding techniques to improve efficiency or automate design and analysis methodologies.
• Leverage AI tools to automate the tools and workflow.
• Applying Artificial Intelligence in workflows to improve build efficiency.

Benefits

Micron offers a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays.

Job Profile(s)

Systems Design Engineering MTS

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.