MTS DRAM ASIC Architect

1840 Micron Tech. OP India LLP; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

1840 Micron Tech. OP India LLP is seeking a Member of Technical Staff for their DRAM ASIC Architecture team. The role emphasizes providing senior level architectural leadership for ASIC and logic-based DRAM solutions, focusing on high performance and energy efficiency.

The ideal candidate will have around 15 years of experience, a strong background in high-speed digital logic design, and the ability to influence cross-functional decisions. Responsibilities include leading architectural trade-offs and serving as a mentor.

Qualifications

• Around 15 years of experience in the relevant field.
• Experience leading technical definition across design teams.
• Ability to work independently and drive own goals.

Responsibilities

• Lead architectural trade-off analysis across DRAM and ASIC logic.
• Drive architectural analysis including PPA evaluation.
• Serve as a technical mentor and architectural authority.

Skills

High speed digital logic design

Architectural trade-offs

Technical leadership

Micro-architectural reviews

Mentoring

Education

Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master’s or PhD degree in relevant engineering field (preferred)

Job description

Role Overview

The DRAM ASIC Architecture team defines silicon level architectures that extend and differentiate the value of Micron’s DRAM products. The team works across technology generations and product lines, collaborating closely with design, product, systems, and ecosystem partners to deliver scalable, reliable, and high-performance memory solutions aligned with customer and market needs. As a Member of Technical Staff, you will provide senior level architectural leadership for ASIC and logic-based DRAM solutions that emphasize high bandwidth, energy efficiency, scalability, and reliability. This role spans near‑term product execution and long‑term technology direction, with architectural ownership over decisions that impact bandwidth density, latency, RAS, and system observability.

Key Responsibilities

• Lead architectural trade‑off analysis across DRAM silicon, ASIC logic, packaging constraints, and system integration considerations – accounting for power delivery, thermals, signal integrity, and form factor limitations.
• Influence functional partitioning and interface definition across DRAM devices and logic die to optimize performance, power, and scalability.
• Drive architectural analysis including PPA evaluation, IO timing considerations, and scalability paths for next‑generation DRAM products.
• Perform micro‑architectural, RTL, and design reviews, along with verification and coverage reviews, to ensure high‑quality execution and first‑silicon success & guide mitigation strategies in collaboration with design and validation teams.
• Influence cross‑functional decisions through clear reasoning, data‑driven analysis, and deep architectural insight.
• Serve as a technical mentor and architectural authority for execution teams, elevating technical rigor and design quality.

Minimum Qualifications

• Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with around 15 years of experience.
• Must have worked on uArch/Arch of SoC or Subsystems – with good work experience leading technical definition across peers & design teams.
• High speed digital logic design experience is a must.
• Familiarity with HIP/Analog blocks usage & integration trade‑offs.
• DRAM Architecture knowledge includes deep understanding of architectural tradeoffs affecting bandwidth, latency, power efficiency, and reliability (RAS is a strong plus).
• Must have demonstrated technical leadership, reviews & mentoring in the past, be able to work independently, self‑learning & driving own goals.
• Ability to work in ambiguity, make reasonable assumptions and validate them through definition cycle.
• Be able to take critical feedback – both technical and non‑technical and drive resolutions with an open mind.
• Guide/mentor micro‑architects/designers, perform review of uArch, RTL, test plans and test coverage.

Preferred Qualifications

• Master’s or PhD degree (or equivalent experience) in a relevant engineering or computer science field.
• Experience on multi‑die interfaces is a plus.
• Experience collaborating across multiple technical domains such as DRAM silicon, ASIC logic, packaging, high‑speed interfaces, or system architecture.
• Experience engaging with customers, ecosystem partners, or industry standards organizations (e.g., JEDEC).
• Demonstrated technical leadership across multiple projects or product generations.
• Familiarity with system‑level tradeoffs involving performance, power, signal integrity, thermals, or cost.

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.