MTS, DDR Design Verification (AI2494)

SiMa.ai; Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

SiMa.ai in Bangalore, India, seeks a MTS DDR Design Verification Engineer to define and develop verification methodology for the MLSoC DDR block. You will create test plans, test benches (drivers, monitors, checkers) and test cases, and run plans to verify DDR functionality, performance and coverage.

You will collaborate with Architecture, RTL/uArch and cross‑functional teams in a full-time on-site role. The successful candidate has 8–10+ years in SoC design verification with SystemVerilog, UVM,

Qualifications

• BS in Computer Science/EE with 10+ years or MS with 8+ years in SoC design verification.
• Experience with block level, cluster level or chip/SoC level verification.
• Proficiency in system verilog, UVM, constrained random and coverage driven verification methodology.
• DDR controller and/or DDR-IO verification experience is a must.

Responsibilities

• Define and develop verification methodology for SiMa.ai’s MLSoC DDR block.
• Develop DDR test plans, test-benches (drivers, monitors, checkers/scoreboard) and test cases.
• Execute test plans to verify DDR functionality, performance and coverage.
• Collaborate with Architecture, RTL/uArch, and cross-functional teams. Participate in DDR bring up on MLSoC Silicon in the lab.

Skills

SystemVerilog

UVM

Constrained Random

Coverage-Driven Verification

DDR Controller Verification

LPDDR5 Knowledge

DDR/LPDDR IP Verification

Test-benches

Python/Perl Scripting

Debugging & Problem Solving

Education

Bachelor's degree in Computer Science/Electrical Engineering

MS in Computer Science/EE

Tools

Python

Perl

UVM Library

Job description

Job Title: MTS, DDR Design Verification

Job Location: Bangalore, India (This position requires a full-time, on-site presence in our Bangalore, India Office)

Job ID: AI2494

Job Description

As the DDR Design Verification Engineer, you will participate in definition and develop the verification methodology for SiMa.ai’s MLSoC. You will be responsible for developing DDR test plans, test-benches (drivers, monitors and checkers/scoreboard etc..) and test cases. You will be executing test plans to verify the MLSoC - DDR functionality, performance and coverage analysis. You will work closely with the Architecture, RTL/uArch, and cross-functional teams. Opportunity to participate on DDR bring up on MLSoC Silicon in the lab.

Required Background

• BS in Computer Science/EE with 10+ years of experience or MS in computer science/EE with 8+ years of experience in SoC design verification.
• Experience with block level, cluster level or chip/SoC level verification.
• Proficiency in system verilog, UVM, constrained random and coverage driven verification methodology.
• DDR controller and/or DDR-IO verification experience is a must.
• Very good understanding of LPDDR JDEC specifications preferably for LPDDR5.
• Good understanding of DDR controller and phy functionality.
• Experience with development of test bench components, test plans for DDR/LPDDR IP verification.
• Good system verilog programming, debug and problem solving skills.
• Scripting languages, python or Perl is a plus.

Personal Attributes

Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.