Lead Engineer - DFT

Quest Global; Ahmedabad District; On-site; INR 1,500,000 - 3,000,000; Full time

Job summary

Quest Global in India is seeking an engineer to design and implement DFT techniques for complex SOCs, including Memory BIST, boundary scan, on-chip compression, At-speed Scan, and related test modes to improve testability and product reliability.

You will generate test vectors (Stuck-at, At-speed, Path delay, SDD, IDDQ, Bridging), verify gate-level timing, and collaborate with cross-functional teams to drive new DFT methodologies, while mentoring junior members to strengthen internal capability.

Responsibilities

• Design and implement DFT techniques for complex SOCs, including Memory BIST, boundary scan, on-chip compression, At-speed Scan, and related test modes to improve testability and product reliability.
• Generate and verify test vectors (Stuck-at, At-speed, Path delay, SDD, IDDQ, Bridging) with high coverage and gate-level timing.

Job description

Job Requirements

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Job Requirements

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Key Responsibilities

• Will be responsible for Designing and Implementing DFT techniques. (Memory BIST/Scan /On-Chip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/Logic BIST) on complex SOCs to improve testability. Test Modes implementation and verification, scan insertion including on-chip compression.. Implementing, integrating and verifying memory BIST and boundary scan . Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test coverage and simulations at gate level with timing (SDF). Basic understanding of complete SOC design and flow.Cross functional teams interaction for issue resolution. Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability. Mentoring new team member. We are looking for a candidate with these specific personal characteristic and qualifications.

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.