Lead – Clocking circuit Design Engineer

Phytau Semiconductors; Bengaluru; On-site; INR 1,800,000 - 2,800,000; Full time

Job summary

Phytau Semiconductors is seeking a hands-on Lead Clocking Design Engineer to drive design and development of high-performance clocking circuits for advanced semiconductor products. You will lead architecture-to-silicon efforts, mentor engineers, and collaborate cross-functionally.

Required is 5–8 years in analog/mixed-signal IC design with hands-on clocking experience, Cadence tools, and strong ownership. The role is based in India and requires on-site engagement.

Qualifications

• Strong fundamentals in analog and mixed-signal IC design.
• Hands-on experience with clocking circuits from architecture to silicon.
• Experience with PLL/DLL/CTRs and high-speed clocking techniques.

Responsibilities

• Lead design of clocking blocks from architecture to silicon.
• Develop and optimize PLL/DLL/ILO/VCO clocking circuits.
• Perform transistor-level design, simulations, and post-layout verification.
• Analyze jitter, phase noise, frequency accuracy, and timing performance.
• Drive layout reviews and parasitic-aware optimization.
• Support silicon bring-up and debug, mentor junior engineers.

Skills

Clocking design

Analog/mixed-signal

PLL fundamentals

Cadence Virtuoso/Spectre

High-speed circuit design

Ownership & leadership

Education

B.E./B.Tech / M.E./M.Tech (Electronics/Electrical)

Tools

Cadence Virtuoso/Spectre

Job description

Phytau Semiconductors is a specialist semiconductor design company built around one core strength: solving difficult analog and high-speed silicon problems.

We specialize in Analog, Clocking, and SerDes, with deep expertise in the circuits that determine the performance of modern high-speed chips. Our work spans high-speed SerDes, PLLs, CDRs, injection-locked oscillators, clocking architectures, and precision analog—from architectural decisions down to transistor-level implementation.

We believe the hardest semiconductor problems are rarely solved by circuit design alone. They require a combination of strong fundamentals, architectural insight, attention to implementation, and relentless silicon-oriented debugging. This is the engineering culture we have built at Phytau.

Our engineers take end-to-end ownership—from understanding the system problem and defining the architecture, through circuit design, simulation, layout interaction, post-layout optimization, and silicon bring-up.

We partner with semiconductor companies that need deep analog expertise without compromising on execution. Whether it is pushing the limits of speed, jitter, power, or performance, Phytau brings the technical depth and ownership needed to turn challenging specifications into working silicon.

We don't aim to be the largest design team. We aim to be the team you call when the silicon problem is hard.

Experience: 5–8 Years

Location: India

Employment Type: Full-time

About the Role

We are looking for a hands-on Lead Clocking Design Engineer to lead the design and development of high-performance clocking circuits and systems for advanced semiconductor products. The role involves technical leadership, circuit design, system-level analysis, and cross-functional collaboration.

Key Responsibilities

• Lead design of clocking circuits and systems from architecture to silicon.
• Develop and optimize high-performance PLL, DLL, ILO, VCO, clock buffer, divider, and clock distribution circuits.
• Perform transistor-level design, simulation, PVT analysis, Monte Carlo, and post-layout verification.
• Analyze jitter, phase noise, frequency accuracy, locking range, power, and timing performance.
• Drive layout reviews and parasitic-aware design optimization.
• Support silicon bring-up, characterization, and debug.
• Mentor junior engineers and drive technical design reviews.

Preferred Clocking Design Experience

Experience in one or more of the following:

• PLLs / Fractional-N PLLs
• DLLs and CDRs
• Ring and LC VCOs
• High-speed clock buffers and dividers
• Clock distribution and clock-tree design
• Phase interpolators and delay lines
• Frequency generation and synchronization circuits
• High-speed SerDes clocking
• Clock and jitter measurement techniques

Required Technical Skills

• Strong fundamentals in analog and mixed-signal IC design.
• Strong understanding of PLL/clocking fundamentals, feedback, stability, noise, jitter, and phase noise.
• Hands-on experience with Cadence Virtuoso/Spectre or equivalent tools.
• Experience with PVT, Monte Carlo, transient, AC/noise, and post-layout simulations.
• Good understanding of high-speed circuit design and analog layout considerations.

Leadership Responsibilities

• Own assigned clocking blocks and drive execution from architecture to silicon.
• Provide technical guidance and mentorship to junior engineers.
• Conduct circuit and design reviews.
• Identify technical risks and drive their resolution.
• Collaborate with system, layout, verification, and digital teams.

Education

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, or a related field.

Experience

5–8 years of industry experience in Analog/Mixed-Signal IC Design, preferably with hands-on experience in clocking circuits and systems.

What We Are Looking For

• Strong hands-on clocking/analog designer with an ownership mindset.
• Ability to independently take designs from architecture to silicon.
• Strong circuit-level analysis and debugging skills.
• Ability to mentor engineers while remaining actively involved in design.
• Good communication and cross-functional collaboration skills.

Good to Have

• Experience with advanced CMOS/FinFET technologies.
• Experience with high-speed SerDes and data-converter clocking.
• Silicon bring-up and characterization experience.
• Experience with 20+ GHz clocking, high-speed I/O, or low-jitter clock generation.
• Knowledge of clocking-related measurement and characterization techniques.